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AM4376, AM4377, AM4378, AM4379
SPRS851B –JUNE 2014–REVISED APRIL 2015
AM437x Sitara™ Processors
1 Device Overview
1.1 Features
1
– Emulation and Debug
• Highlights
• JTAG
– Sitara™ ARM
®
Cortex
®
-A9 32-Bit RISC
Processor With Processing Speed up to 1000
• Embedded Trace Buffer
MHz
– Interrupt Controller
• NEON™ SIMD Coprocessor and Vector
• On-Chip Memory (Shared L3 RAM)
Floating Point (VFPv3) Coprocessor
– 256KB of General-Purpose On-Chip Memory
• 32KB of Both L1 Instruction and Data Cache
Controller (OCMC) RAM
• 256KB of L2 Cache or L3 RAM
– Accessible to All Masters
– 32-Bit LPDDR2, DDR3, and DDR3L Support
– Supports Retention for Fast Wakeup
– General-Purpose Memory Support (NAND,
– Up to 512KB of Total Internal RAM
NOR, SRAM) Supporting up to 16-Bit ECC
(256KB of ARM Memory Configured as L3 RAM
+ 256KB of OCMC RAM)
– SGX530 Graphics Engine
• External Memory Interfaces (EMIFs)
– Display Subsystem
– DDR Controllers:
– Programmable Real-Time Unit Subsystem and
Industrial Communication Subsystem (PRU-
• LPDDR2: 266-MHz Clock (LPDDR2-533
ICSS)
Data Rate)
– Real-Time Clock (RTC)
• DDR3 and DDR3L: 400-MHz Clock (DDR-
– Up to Two USB 2.0 High-Speed Dual-Role
800 Data Rate)
(Host or Device) Ports With Integrated PHY
• 32-Bit Data Bus
– 10, 100, and 1000 Ethernet Switch Supporting
• 2GB of Total Addressable Space
up to Two Ports
• Supports One x32, Two x16, or Four x8
– Serial Interfaces:
Memory Device Configurations
• Two Controller Area Network (CAN) Ports
• General-Purpose Memory Controller (GPMC)
• Six UARTs, Two McASPs, Five McSPIs,
– Flexible 8- and 16-Bit Asynchronous Memory
Three I
2
C Ports, One QSPI, and One HDQ
Interface With up to Seven Chip Selects (NAND,
or 1-Wire
NOR, Muxed-NOR, and SRAM)
– Security
– Uses BCH Code to Support 4-, 8-, or 16-Bit
• Crypto Hardware Accelerators (AES, SHA,
ECC
RNG, DES, and 3DES)
– Uses Hamming Code to Support 1-Bit ECC
• Secure Boot
• Error Locator Module (ELM)
– Two 12-Bit Successive Approximation Register
– Used With the GPMC to Locate Addresses of
(SAR) ADCs
Data Errors From Syndrome Polynomials
– Up to Three 32-Bit Enhanced Capture Modules Generated Using a BCH Algorithm
(eCAPs)
– Supports 4-, 8-, and 16-Bit Per 512-Byte Block
– Up to Three Enhanced Quadrature Encoder Error Location Based on BCH Algorithms
Pulse Modules (eQEPs)
• Programmable Real-Time Unit Subsystem and
– Up to Six Enhanced High-Resolution PWM Industrial Communication Subsystem (PRU-ICSS)
Modules (eHRPWMs)
– Supports Protocols such as EtherCAT
®
,
• MPU Subsystem PROFIBUS
®
, PROFINET
®
, and EtherNet/IP™,
EnDat 2.2, and More
– ARM Cortex-A9 32-Bit RISC Microprocessor
With Processing Speed up to 1000 MHz – Two Programmable Real-Time Units (PRUs)
Subsystems With Two PRU Cores Each
– 32KB of Both L1 Instruction and Data Cache
• Each Core is a 32-Bit Load and Store RISC
– 256KB of L2 Cache (Option to Configure as L3
Processor Capable of Running at 200 MHz
RAM)
• 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of
– 256KB of On-Chip Boot ROM
Instruction RAM With Single-Error Detection
– 64KB of On-Chip RAM
(Parity)
– Secure Control Module (SCM)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 10
- ・ Abmessungen des Paketumrisses on Seite 257 Seite 258
- ・ Markierungsinformationen on Seite 257 Seite 258
- ・ Blockdiagramm on Seite 6 Seite 131 Seite 133 Seite 134 Seite 136
- ・ Beschreibung der Funktionen on Seite 116
- ・ Technische Daten on Seite 3 Seite 101 Seite 102 Seite 103 Seite 104
- ・ Anwendungsbereich on Seite 4 Seite 208 Seite 261
- ・ Elektrische Spezifikation on Seite 62 Seite 109 Seite 110 Seite 111
- ・ Teilenummernliste on Seite 108
