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AN-1002
APPLICATION NOTE
One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Te l: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
The AD9548 as a GPS Disciplined Stratum 2 Clock
by Ken Gentile
Rev. 0 | Page 1 of 16
INTRODUCTION
The synchronous optical network (SONET) is the backbone
of most of the world’s day-to-day communication systems. Its
stringent requirements with regard to the clocking signals that
synchronize the system allow for reliable transmission of data
across a multitude of interlinked systems spread out around
the globe. The system is comprised of a hierarchy of precision
timing units categorized according to their accuracy and drift
performance criteria, that is, the stratum levels. Stratum 1 is the
most demanding level with timing accuracies only possible with
atomic clocks. The timing performance requirements become
more relaxed with increasing stratum level numbers (Stratum 2,
Stratum 3E, Stratum 3, Stratum 4). Focusing on Stratum 2, there
are two primary requirements (see the clock requirements sum-
mary table in the GR-1244-CORE SONET standard, “Clocks for
the Synchronized Network: Common Generic Criteria” avail-
able from Telcordia Technologies):
• 1.6 × 10
−8
or 16 part per billion (ppb) free-run accuracy
over a period of 20 years with no outside reference
• 1 × 10
−10
or 0.1 ppb stability over a period of 24 hours in
holdover mode
The holdover stability requirement implies a certain cumulative
time error (CTE), for which an estimate is possible according to
the following equation from C. W.T. Nicholls’ and G.C. Carleton’s
paper, “Adaptive OCXO Drift Correction Algorithm” (see the
References section):
f/f
0
= t/T
where:
f/f
0
is the static frequency stability.
T is the holdover period.
t is the CTE estimate.
Based on the Stratum 2 specification, for which f/f
0
= 10
−10
and
T = 86,400 seconds (24 hours), the calculation yields a CTE of
8.64 s/day.
The holdover requirement adds significant cost to a Stratum 2
timing unit because the full burden of the stability requirement
falls on the clock’s local timing source. Assuming the local clock
source is an oven-controlled crystal oscillator (OCXO), then
only the most stable (that is, expensive) ones are viable options.
Consequently, as the number of Stratum 2 compliant installa-
tions increases so does the pressure to find a low cost solution.
This application note proposes the feasibility of a relatively low
cost solution using the Analog Devices, Inc. AD9548 digital
phase-lock loop (PLL). The solution is based on Nicholls and
Carleton’s paper and demonstrates the ability to provide hold-
over stability of 0.017 ppb (a CTE of 1.5 s/day) using an
OCXO with a stability of 0.45 ppb (a CTE of 38.9 s/day).
Note that the 0.45 ppb OCXO stability comes from 0.4 ppb for
temperature and 0.05 ppb for aging. The Nicholls and Carleton
paper describes an adaptive drift correction algorithm (here-
after referred to as the N/C system) that compensates for the
OCXO’s drift characteristics during holdover.
Before proceeding, read Appendix A for a synopsis of the
N/C system. Becoming familiar with the N/C system is helpful
because this system is compared with the proposed AD9548-
based system (hereafter referred to as the proposed system)
occurs throughout the remainder of this document.
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