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Application Report
SNAA070A–September 2009–Revised May 2013
AN-2001 Daisy Chaining Precision DACs
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ABSTRACT
It is not uncommon for the system designer to face a quagmire of reconciling the system complexity with
the desire to keep the system footprint small. One specific example that often arises in the context of
small system footprint is the need for single master controller to communicate with a number of slave
devices. This is not much of a problem if the master controller has multiple I/O resources available, and
the routing of individual busses to the slave devices can be accommodated by ample board space.
Challenge arises when the master controller has only one I/O port available, and the signal routing space
is scarce. In these cases, Daisy Chaining of slave devices may be the solution to consider.
Contents
1 Introduction .................................................................................................................. 2
2 Revisiting Micro Power DACs' Digital Interface: 1, 2 and 4 Channel Devices ...................................... 2
3 Revisiting Eight-Channel DACs' Digital Interface ....................................................................... 3
4 Flexible DAC Channel Expansion ........................................................................................ 4
5 Conclusion ................................................................................................................... 6
List of Figures
1 Typical Digital Interface Connectivity..................................................................................... 2
2 Typical Bus Cycle........................................................................................................... 2
3 Typical Controller to N 8-Channel DACs Interface: Daisy Chain..................................................... 3
4 8-Channel DAC Bus Cycle ................................................................................................ 4
5 Flexible DAC Channel Expansion ........................................................................................ 4
6 Flexible DAC Bus Cycle.................................................................................................... 5
7 Data Register Contents Resulting From Bus Cycle Shown in Figure 6 ............................................. 6
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SNAA070A–September 2009–Revised May 2013 AN-2001 Daisy Chaining Precision DACs
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