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Application Report
SNLA116A–May 2009–Revised April 2013
AN-1963 IEEE 1588 Synchronization Over Standard
Networks Using the DP83640
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ABSTRACT
This application report describes a method of synchronization that provides much more accurate
synchronization in systems with larger PDV. The method described attempts to detect minimum delays, or
'lucky packets'. The method also takes advantage of the DP83640 clock control mechanism to separately
control clock rate and time corrections, minimizing overshoot or wild swings in the accuracy of the clock
time.
Contents
1 Introduction .................................................................................................................. 2
2 Background .................................................................................................................. 2
2.1 Proposed Algorithm ................................................................................................ 3
3 Test Platform ................................................................................................................ 5
4 Test Results ................................................................................................................. 6
4.1 Single Switch Results ............................................................................................. 6
4.2 Multiple Switch Testing ............................................................................................ 7
4.3 Other Testing Results ............................................................................................. 8
5 Additional Opportunities .................................................................................................... 8
6 Conclusions .................................................................................................................. 9
7 References ................................................................................................................... 9
List of Figures
1 Basic PTP Timing Diagram................................................................................................ 2
2 MTIE Plot For Basic Algorithm, 80% Traffic Utilization ................................................................ 3
3 Rate Correction Diagram................................................................................................... 4
4 Test Platform ................................................................................................................ 6
5 MTIE Plot for One Switch Tests........................................................................................... 7
6 TDEV Plot for One Switch Tests.......................................................................................... 7
7 MTIE Plot for Three Switch Tests......................................................................................... 8
8 TDEV Plot for Three Switch Tests........................................................................................ 8
List of Tables
1 PPS Results For Single Switch Tests.................................................................................... 6
2 PPS Results for Three Switch Tests ..................................................................................... 7
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SNLA116A–May 2009–Revised April 2013 AN-1963 IEEE 1588 Synchronization Over Standard Networks Using the
DP83640
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