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EPM1270F256C5N Anwendungshinweis

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© August 2009 Altera Corporation MAX II Device Handbook
Section I. MAX II Device Family Data
Sheet
This section provides designers with the data sheet specifications for MAX
®
II devices.
The chapters contain feature definitions of the internal architecture, Joint Test Action
Group (JTAG) and in-system programmability (ISP) information, DC operating
conditions, AC timing parameters, and ordering information for MAX II devices.
This section includes the following chapters:
Chapter 1, Introduction
Chapter 2, MAX II Architecture
Chapter 3, JTAG and In-System Programmability
Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices
Chapter 5, DC and Switching Characteristics
Chapter 6, Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information about when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the complete handbook.
Verzeichnis

EPM1270F256C5N Datenblatt-PDF

EPM1270F256C5N Datenblatt PDF
Altera
10 Seiten, 136 KB
EPM1270F256C5N Benutzerreferenzhandbuch
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2 Seiten, 102 KB
EPM1270F256C5N Anderes Datenblatt
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86 Seiten, 1219 KB
EPM1270F256C5N Anwendungshinweis
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88 Seiten, 827 KB
EPM1270F256C5N Eigenschaften Beschreibung Parameter
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6 Seiten, 87 KB

EPM1270F256C5 Datenblatt-PDF

EPM1270F256C5
Datenblatt PDF
Altera
CPLD MAX II Family 980 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 256Pin FBGA
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EPM1270F256C5N
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CPLD MAX II Family 980 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 256Pin FBGA
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