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AN1782/0905 1/7
Rev. 2.0
AN1782
APPLICATION NOTE
STR71X I2C
COMMUNICATION WITH M24CXX EEPROM
INTRODUCTION
This application note gives an example of how to use the STR71x I2C peripheral to communi-
cate with an I2C Protocol-Compatible Electrically Erasable Programmable Read Only Mem-
ory (EEPROM). The example uses the M24C08 EEPROM from STMicroelectronics.
The implemented software manages read and write operations between the STR71x I2C
interface and the M24C08.
1 STR71X I2C PERIPHERAL
The STR71x I2C peripheral provides both multi master and slave functions, and controls all
I2C bus-specific sequencing, protocol, arbitration and timing. It also provides the transfer
problem detection feature. The speed of the I2C interface may be selected between standard
(0-100KHz) and fast I2C (100-400KHz).
The STR71x provides two I2C interfaces I2C0 and I2C1.
Only the master characteristics of the STR71x I2C are needed to manage the communication
sequencing with EEPROM, which acts as a slave.
In this application, only the single master mode is used without error management.
To implement the I2C protocol, only 2 bidirectional lines are required, SCL (Serial Clock Line),
which carries the synchronization clock and SDA (Serial Data Line), which carries the bit to be
transmitted. This line is driven by the device that sends the data.
The corresponding port pins have to be configured as alternate function open drain.
Please refer to the STR71x reference manual for more details.
2 M24CXX EEPROM
The M24Cxx families of EEPROM are compatible with the I2C protocol. This EEPROM family
includes a range of different devices. Table 1 displays the size, the number of devices that can
be connected to the I2C bus and the number of blocks in each device.
Table 1. M24Cxx EEPROMs family characteristics
Device Size (Kbit) Devices per Bus Number of Blocks
M24C01 1 8 1
1
