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Maxim > Design Support > Technical Documents > Application Notes > Communications Circuits > APP 4457
Maxim > Design Support > Technical Documents > Application Notes > Measurement Circuits > APP 4457
Maxim > Design Support > Technical Documents > Application Notes > Power-Supply Circuits > APP 4457
Keywords: PLL, clock generator, power supply noise rejection, PSRR, low jitter, deterministic jitter,
phase-locked loop, power spectrum, phase noise spectrum, frequency domain spur measurements
APPLICATION NOTE 4457
Assess Power-Supply Noise Rejection in Low-
Jitter PLL Clock Generators
By: John Abcarius
Sharon Wang
Jun 03, 2009
Abstract: This article discusses the effects of power-supply noise interference on PLL-based clock
generators, and describes several measurement techniques for evaluating the resulting deterministic jitter
(DJ). Derived relationships show how frequency-domain spur measurements can be used to evaluate
timing-jitter behavior. Laboratory bench-test results are used to compare the measurement techniques,
and demonstrate how to reliably assess the power-supply noise rejection (PSNR) performance of a
reference clock generator.
This article was also featured in Maxim's Engineering Journal, vol. 66 (PDF, 3.07MB).
A version of this article was published online by Electronic Design magazine, March 27, 2009.
Clock generators that employ PLLs are widely used in network equipment for generating high-precision
and low-jitter reference clocks or for maintaining a synchronized network operation. Most clock oscillators
give their jitter or phase-noise specification using an ideal, clean power supply. In a practical system
environment, however, the power supply can suffer from interference due to on-board switching supplies
or noisy digital ASICs. To achieve the best performance in a system design, it is important to understand
the effects of such interference.
First we will examine the basic power-supply noise rejection (PSNR) characteristics of a PLL-based
clock generator. We will then explain how to extract timing-jitter information from measurements taken in
the frequency domain. These techniques are then applied and several different measurement
methodologies are compared using lab bench testing. Finally, we will summarize the merits of the
preferred approach.
PSNR Characteristics of PLL Clock Generators
A typical PLL clock generator is shown in Figure 1. Since the output driver can have very different
PSNR performance for different types of logic interfaces, the following analysis will focus on the impact
of supply noise on the PLL itself.
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