herunterladen
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 5
1 Publication Order Number:
MC100LVEL59/D
MC100LVEL59
3.3V ECL Triple 2:1
Multiplexer
Description
The MC100LVEL59 is a 3.3 V triple 2:1 multiplexer with
differential outputs. The output data of the multiplexers can be
controlled individually via the select inputs or as a group via the
common select input. The flexible selection scheme makes the device
useful for both data path and random logic applications.
Features
• Individual or Common Select Controls
• 500 ps Typical Propagation Delays
• ESD Protection: > 2 kV HBM
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Q Output will Default LOW with Inputs Open or at V
EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity: Level 3 (Pb-free)
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−O @ 0.125 in,
Oxygen Index 28 to 34
• Transistor Count = 182 devices
• These Devices are Pb-Free and are ROHS Compliant
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D
.
MARKING DIAGRAM*
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
SOIC−20 WB
DW SUFFIX
CASE 751D
20
1
100LVEL59
AWLYYWWG
ORDERING INFORMATION
Device Package Shipping
MC100LVEL59DWG SOIC−20 WB
(Pb-Free)
38 Units/Tube
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 2
- ・ Abmessungen des Paketumrisses on Seite 5
- ・ Paket-Footprint-Pad-Layout on Seite 5
- ・ Teilenummerierungssystem on Seite 1 Seite 5
- ・ Markierungsinformationen on Seite 1 Seite 4 Seite 5
- ・ Typisches Anwendungsschaltbild on Seite 2
- ・ Technische Daten on Seite 4
- ・ Teilenummernliste on Seite 2
