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© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 10
1 Publication Order Number:
MC14013B/D
MC14013B
Dual Type D Flip-Flop
The MC14013B dual type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each flip−flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q
). These devices may be used as shift register
elements or as type T flip−flops for counter and toggle applications.
Features
• Static Operation
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge−Clocked Flip−Flop Design
• Logic State is Retained Indefinitely with Clock Level either High or
Low; Information is Transferred to the Output only on the
Positive−going Edge of the Clock Pulse
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD4013B
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage Range −0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±10 mA
P
D
Power Dissipation, per Package
(Note 1)
500 mW
T
A
Ambient Temperature Range −55 to +125 °C
T
stg
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature
(8−Second Soldering)
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
MARKING DIAGRAMS
SOIC−14
TSSOP−14
1
14
14013BG
AWLYWW
14
013B
ALYW G
G
1
14
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
SOEIAJ−14
1
14
MC14013B
ALYWG
S
ee detailed ordering and shipping information in the package
d
imensions section on page 2 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
(Note: Microdot may be in either location)
SOIC−14
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
SOEIAJ−14
F SUFFIX
CASE 965
11
12
13
14
8
9
105
4
3
2
1
7
6
R
B
C
B
Q
B
Q
B
V
DD
S
B
D
B
R
A
C
A
Q
A
Q
A
V
SS
S
A
D
A
PIN ASSIGNMENT
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 1
- ・ Abmessungen des Paketumrisses on Seite 6 Seite 7 Seite 8
- ・ Paket-Footprint-Pad-Layout on Seite 6 Seite 7
- ・ Teilenummerierungssystem on Seite 1 Seite 2 Seite 8
- ・ Markierungsinformationen on Seite 1 Seite 8
- ・ Blockdiagramm on Seite 2
- ・ Typisches Anwendungsschaltbild on Seite 4 Seite 5
- ・ Technische Daten on Seite 2
- ・ Anwendungsbereich on Seite 1 Seite 2 Seite 5
- ・ Elektrische Spezifikation on Seite 3
- ・ Teilenummernliste on Seite 1
