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© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 10
1 Publication Order Number:
MC14503B/D
MC14503B
Hex Non-Inverting 3-State
Buffer
The MC14503B is a hex non−inverting buffer with 3−state outputs,
and a high current source and sink capability. The 3−state outputs
make it useful in common bussing applications. Two disable controls
are provided. A high level on the Disable A input causes the outputs of
buffers 1 through 4 to go into a high impedance state and a high level
on the Disable B input causes the outputs of buffers 5 and 6 to go into
a high impedance state.
Features
• 3−State Outputs
• TTL Compatible − Will Drive One TTL Load Over Full Temperature
Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Two Disable Controls for Added Versatility
• Pin for Pin Replacement for MM80C97 and 340097
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
) (Note 1)
Parameter
Symbol Value Unit
DC Supply Voltage Range V
DD
−0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V
in
, V
out
−0.5 to V
DD
+ 0.5
V
Input Current (DC or Transient) per Pin I
in
±10 mA
Output Current (DC or Transient) per Pin I
out
±25 mA
Power Dissipation, per Package (Note 2) P
D
500 mW
Ambient Temperature Range T
A
−55 to +125 °C
Storage Temperature Range −65 to +150 °C
Lead Temperature (8−Second Soldering) 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Maximum Ratings are those values beyond which damage to the device may
occur.
2. Temperature Derating:
“D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
MARKING DIAGRAM
SOIC−16
D SUFFIX
CASE 751B
1
16
14503BG
AWLYWW
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
1
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
IN 5
OUT 6
IN 6
V
DD
OUT 4
IN 4
OUT 5
IN 2
OUT 1
IN 1
DIS A
V
SS
OUT 3
IN 3
OUT 2
DIS B
TRUTH TABLE
Appropriate
Disable
In
n
Input Out
n
00 0
10 1
X 1 High
Impedance
X = Don’t Care
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 1
- ・ Abmessungen des Paketumrisses on Seite 5
- ・ Paket-Footprint-Pad-Layout on Seite 5
- ・ Teilenummerierungssystem on Seite 1 Seite 4 Seite 5
- ・ Markierungsinformationen on Seite 1 Seite 5
- ・ Typisches Anwendungsschaltbild on Seite 2
- ・ Technische Daten on Seite 4
- ・ Anwendungsbereich on Seite 1 Seite 4
- ・ Elektrische Spezifikation on Seite 2
- ・ Teilenummernliste on Seite 1
