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© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 9
1 Publication Order Number:
MC14512B/D
MC14512B
8-Channel Data Selector
The MC14512B is an 8−channel data selector constructed with
MOS P−channel and N−channel enhancement mode devices in a
single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
sequence generation.
Features
• Diode Protection on All Inputs
• Single Supply Operation
• 3−State Output (Logic “1”, Logic “0”, High Impedance)
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• These Devices are Pb−Free and are RoHS Compliant
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Parameter Symbol Value Unit
DC Supply Voltage Range V
DD
−0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V
in
, V
out
−0.5 to V
DD
+ 0.5
V
Input or Output Current
(DC or Transient) per Pin
I
in
, I
out
± 10 mA
Power Dissipation, Per Package (Note 1) P
D
500 mW
Ambient Temperature Range T
A
−55 to +125 °C
Storage Temperature Range T
stg
−65 to +150 °C
Lead Temperature (8−Second Soldering) T
L
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
G = Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
1
16
14512BG
AWLYWW
16
1
MC14512BCP
AWLYYWWG
1
1
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 2
- ・ Abmessungen des Paketumrisses on Seite 6 Seite 7
- ・ Paket-Footprint-Pad-Layout on Seite 7
- ・ Teilenummerierungssystem on Seite 1 Seite 2 Seite 7
- ・ Markierungsinformationen on Seite 1 Seite 7
- ・ Typisches Anwendungsschaltbild on Seite 5
- ・ Technische Daten on Seite 2
- ・ Anwendungsbereich on Seite 1 Seite 2
- ・ Elektrische Spezifikation on Seite 3
