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© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 10
1 Publication Order Number:
MC14512B/D
MC14512B
8-Channel Data Selector
The MC14512B is an 8−channel data selector constructed with
MOS P−channel and N−channel enhancement mode devices in
a single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
sequence generation.
Features
• Diode Protection on All Inputs
• Single Supply Operation
• 3−State Output (Logic “1”, Logic “0”, High Impedance)
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Parameter
Symbol Value Unit
DC Supply Voltage Range V
DD
−0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V
in
, V
out
−0.5 to V
DD
+ 0.5
V
Input or Output Current
(DC or Transient) per Pin
I
in
, I
out
± 10 mA
Power Dissipation, Per Package (Note 1) P
D
500 mW
Ambient Temperature Range T
A
−55 to +125 °C
Storage Temperature Range T
stg
−65 to +150 °C
Lead Temperature (8−Second Soldering) T
L
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
G = Pb−Free Package
MARKING DIAGRAM
SOIC−16
D SUFFIX
CASE 751B
1
16
14512BG
AWLYWW
1
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
B
C
Z
DIS
V
DD
X7
INH
A
X3
X2
X1
X0
V
SS
X6
X5
X4
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 1
- ・ Abmessungen des Paketumrisses on Seite 6
- ・ Paket-Footprint-Pad-Layout on Seite 6
- ・ Teilenummerierungssystem on Seite 1 Seite 3 Seite 6
- ・ Markierungsinformationen on Seite 1 Seite 6
- ・ Typisches Anwendungsschaltbild on Seite 5
- ・ Technische Daten on Seite 3
- ・ Anwendungsbereich on Seite 1 Seite 3
- ・ Elektrische Spezifikation on Seite 2
- ・ Teilenummernliste on Seite 1
