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44-pin LQFP
Case:
10 x 10 mm
2
64-pin LQFP
Case:
10 x 10 mm
2
48-pin LQFP
Case:
7 x 7 mm
2
Freescale Semiconductor
Technical Data
Document Number: MC56F825X
Rev. 4, 06/2014
© Freescale Semiconductor, Inc., 2009-2011, 2014. All rights reserved.
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
MC56F825x/MC56F824x
The MC56F825x/MC56F824x is a member of the 56800E
core-based family of digital signal controllers (DSCs). It
combines, on a single chip, the processing power of a DSP
and the functionality of a microcontroller with a flexible set of
peripherals to create a cost-effective solution. Because of its
low cost, configuration flexibility, and compact program
code, it is well-suited for many applications. The
MC56F825x/MC56F824x includes many peripherals that are
especially useful for cost-sensitive applications, including:
• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Solar inverters
• Battery chargers and management
• Switched-mode power supplies and power management
•Power metering
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical devices/equipment
• Instrumentation
• Lighting ballast
The 56800E core is based on a modified Harvard-style
architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction
cycle. The MCU-style programming model and optimized
instruction set allow straightforward generation of efficient,
compact DSP and control code. The instruction set is also
highly efficient for C compilers to enable rapid development
of optimized control applications.
The MC56F825x/MC56F824x supports program execution
from internal memories. Two data operands per instruction
cycle can be accessed from the on-chip data RAM. A full set
of programmable peripherals supports various applications.
Each peripheral can be independently shut down to save
power. Any pin, except Power pins and the Reset pin, can also
be configured as General Purpose Input/Outputs (GPIOs).
On-chip features include:
• 60 MHz operation frequency
• DSP and MCU functionality in a unified, C-efficient
architecture
• On-chip memory
– 56F8245/46: 48 KB (24K x 16) flash memory; 6 KB
(3K x 16) unified data/program RAM
– 56F8247: 48 KB (24K x 16) flash memory; 8 KB
(4K x 16) unified data/program RAM
– 56F8255/56/57: 64 KB (32K x 16) flash memory; 8 KB
(4K x 16) unified data/program RAM
• eFlexPWM with up to 9 channels, including 6 channels
with high (520 ps) resolution NanoEdge placement
• Two 8-channel, 12-bit analog-to-digital converters (ADCs)
with dynamic x2 and x4 programmable amplifier,
conversion time as short as 600 ns, and input
current-injection protection
• Three analog comparators with integrated 5-bit DAC
references
• Cyclic Redundancy Check (CRC) Generator
• Two high-speed queued serial communication interface
(QSCI) modules with LIN slave functionality
• Queued serial peripheral interface (QSPI) module
• Two SMBus-compatible inter-integrated circuit (I
2
C) ports
• Freescale’s scalable controller area network (MSCAN) 2.0
A/B module
• Two 16-bit quad timers (2 x 4 16-bit timers)
• Computer operating properly (COP) watchdog module
• On-chip relaxation oscillator: 8 MHz (400 kHz at standby
mode)
• Crystal/resonator oscillator
• Integrated power-on reset (POR) and low-voltage interrupt
(LVI) and brown-out reset module
• Inter-module crossbar connection
• Up to 54 GPIOs
• 44-pin LQFP, 48-pin LQFP, and 64-pin LQFP packages
• Single supply: 3.0 V to 3.6 V
MC56F825x/MC56F824x
Digital Signal Controller
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 15
- ・ Abmessungen des Paketumrisses on Seite 18 Seite 19 Seite 20 Seite 21 Seite 22
- ・ Teilenummerierungssystem on Seite 74 Seite 75
- ・ Blockdiagramm on Seite 8 Seite 9
- ・ Technische Daten on Seite 1 Seite 11 Seite 48 Seite 49 Seite 50
- ・ Elektrische Spezifikation on Seite 53 Seite 54 Seite 56
