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MC74VHC1G50DFT2 Anwendungshinweis - ON Semiconductor

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MC74VHC1G50DFT2 Anwendungshinweis

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Semiconductor Components Industries, LLC, 2003
December, 2003 − Rev. 11
1 Publication Order Number:
MC74VHC1G50/D
MC74VHC1G50
Buffer
The MC74VHC1G50 is an advanced high speed CMOS buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output.
The MC74VHC1G50 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G50 to be used to interface 5.0 V circuits to 3.0 V
circuits.
High Speed: t
PD
= 3.5 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 1 A (Max) at T
A
= 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FET = 104; Equivalent Gate = 26
Figure 1. Pinout (Top View)
V
CC
NC
IN A
OUT Y
GND
IN A
OUT Y
1
Figure 2. Logic Symbol
1
2
3
5
4
FUNCTION TABLE
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
L
H
A Input Y Output
L
H
SC−88A / SOT−353/SC−70
DF SUFFIX
CASE 419A
Pin 1
d = Date Code
VR
d
TSOP−5/SOT−23/SC−59
DT SUFFIX
CASE 483
Pin 1
d = Date Code
VR
d
MARKING
DIAGRAMS
PIN ASSIGNMENT
1
2
3 GND
NC
IN A
4
5V
CC
OUT Y
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MC74VHC1G50DFT2 Datenblatt-PDF

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