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Power Architecture
®
technology, which includes
16 KB of L1 instruction and data caches, dual
integer units and on-chip memory management
units (MMUs).
QUICC Engine Technology
A communications complex, based on
QUICC Engine technology, forms the heart
of the networking capability of the MPC830x
portfolio. The QUICC Engine block contains
several peripheral controllers and a 32-bit
RISC controller. Protocol support is provided
by the main workhorses of the device—the
unified communication controllers (UCCs).
Each of the five UCCs can support a variety
of communication protocols, including 10/100
Mbps Ethernet and high-level data link
control (HDLC). Two of the UCCs can also
support IEEE
®
1588 version-2 time stamping
(MPC8306 configuration only).
System Interface Unit
The MPC8306S and MPC8306 processors
also include a 16-bit double data rate (DDR2)
memory controller, 4 x UARTs, High-Speed
USB 2.0 controller, a 16-bit local bus and two
direct memory access (DMA) channels. In
addition, the MPC8306 also features 4 x CAN
and an enhanced SDHC controller.
In summary, the MPC8306S and MPC8306
devices provide users with a highly integrated,
fully programmable communications
processor for use in many networking and
industrial control applications. This helps
ensure that a cost-effective system solution
can be quickly developed and will offer
flexibility to accommodate new standards
and evolving system requirements.
Typical Applications
• I/O card for low-end base station
• Factory automation
• Industrial control
• Test and measurement equipment
MPC8306/S Features
• High-performance, low-power and cost-
effective communications processor
• The e300 core, built on Power Architecture
technology, with dual integer units enables
more efficient operations to be conducted
in parallel, resulting in a significant
performance improvement
• The single-RISC QUICC Engine
communications module offers a future-
proof solution for next-generation designs
by supporting programmable protocol
termination and network interface
termination to meet evolving protocol
standards
• DDR2 memory controller—one 16-bit
interface up to 266 MHz
• Peripheral interfaces such as 16-bit, 66
MHz local bus interface and High-Speed
USB 2.0, 4 x CAN, 4 x UARTs, enhanced
SDHC controller
Integrated Communications Processors
MPC8306 and MPC8306S
PowerQUICC II Pro Processors
Overview
The MPC8306 and MPC8306S processors
are part of the ultra low-end MPC830x
communications processor portfolio based
on the e300 core architecture. They address
the requirements of networking applications,
including I/O cards for low-end base stations,
residential gateways, modem/routers,
industrial control, factory automation and test
and measurement applications. The MPC830x
portfolio extends current PowerQUICC
offerings, providing similar DMIPS/MHz in
CPU performance, additional functionality
and faster interfaces while maintaining
code compatibility with PowerQUICC I
and PowerQUICC II processors. MPC830x
processors also provide competitive pricing,
low power consumption, compact board
footprint and a time to market advantage
through cost-effective evaluation kits with
optimized BSP and drivers.
Core Complex
The MPC8306 and MPC8306S incorporate
the e300c3 (MPC603e-based) core, built on
MPC8306/S Block Diagram
16-bit DDR2
Controller
e300 Core
Complex
Local Bus
16 KB
D-Cache
16 KB
I-Cache
2 x DUART
I
2
C
Timers
SPI
GPIO
Interrupt Controller
Or
8-bit GPIO
QUICC Engine
Coherent System Bus
Up to
3 x RMII/MII
or
2 x with
IEEE
®
1588
2 x HDLC
/TDM
Accelerators I/O only in MPC8306Core
USB
2.0
4 x
CAN
8-bit
eSDHC
8-bit
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