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Products and specifications discussed herein are subject to change by Micron without notice.
128Mb: x32 SDRAM
Features
PDF: 09005aef80872800/Source: 09005aef80863355 Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MbSDRAMx32_1.fm - Rev. L 1/09 EN
1 ©2001 Micron Technology, Inc. All rights reserved.
Synchronous DRAM
MT48LC4M32B2 – 1 Meg x 32 x 4 banks
For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdram
Features
• PC100 functionality
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
and auto refresh modes
• Self refresh mode (not available on AT devices)
•Auto refresh
– 64ms, 4,096-cycle refresh (15.6µs/row)
(commercial & industrial)
– 16ms, 4,096-cycle refresh (3.9µs/row)
(automotive)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency (CL) of 1, 2, and 3
Notes: 1. Off-center parting line.
2. Consult Micron for availability.
Options Marking
• Configuration
– 4 Meg x 32 (1 Meg x 32 x 4 banks)
4M32B2
•Package – OCPL
1
– 86-pin TSOP II (400 mil)
TG
– 86-pin TSOP II (400 mil) lead-free
P
– 90-ball VFBGA (8mm x 13mm)
F5
–
90-ball VFBGA (8mm x 13mm) lead-free
B5
• Timing (cycle time)
– 6ns (166 MHz)
-6
– 7ns (143 MHz)
-7
•Die revision :G
• Operating temperature range
– Commercial (0° to +70°C)
None
– Industrial (-40° to +85°C) IT
– Automotive (–40°C to +105°C) AT
2
Notes: 1. FBGA Device Decoder: www.micron.com/
decoder.
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed
Grade
Clock
Frequency
Access Time
Setup
Time
Hold
TimeCl = 3
-6 166 MHz 5.5ns 1.5ns 1ns
-7 143 MHz 5.5ns 2ns 1ns
Table 2: Configurations
4 Meg x 32
Configuration
1 Meg x 32 x 4 banks
Refresh count
4K
Row addressing
4K (A0–A11)
Bank addressing
4 (BA0, BA1)
Column addressing
256 (A0–A7)
Table 3: 128Mb (x32) SDRAM Part Numbers
Part Number Architecture
MT48LC4M32B2TG
4 Meg x 32
MT48LC4M32B2P
4 Meg x 32
MT48LC4M32B2F5
1
4 Meg x 32
MT48LC4M32B2B5
1
4 Meg x 32
