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© 2005 Fairchild Semiconductor Corporation DS500270 www.fairchildsemi.com
April 2000
Revised January 2005
NC7WZ32 TinyLogic
UHS Dual 2-Input OR Gate
NC7WZ32
TinyLogic
UHS Dual 2-Input OR Gate
General Description
The NC7WZ32 is a dual 2-Input OR Gate from Fairchild’s
Ultra High Speed Series of TinyLogic
. The device is fabri-
cated with advanced CMOS technology to achieve ultra
high speed with high output drive while maintaining low
static power dissipation over a very broad V
CC
operating
range. The device is specified to operate over the 1.65V to
5.5V V
CC
range. The inputs and output are high impedance
when V
CC
is 0V. Inputs tolerate voltages up to 7V indepen-
dent of V
CC
operating voltage.
Features
■ Space saving US8 surface mount package
■ MicroPak
Pb-Free leadless package
■ Ultra high speed t
PD
2.4 ns Typ into 50 pF at 5V V
CC
■ High output drive ±24 mA at 3V V
CC
■ Broad V
CC
operating range 1.65V to 5.5V
■ Matches the performance of LCX when operated at
3.3V V
CC
■ Power down high impedance inputs/output
■ Overvoltage tolerant inputs facilitate 5V to 3V translation
■ Patented noise/EMI reduction circuitry implemented
Ordering Code:
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Pin Descriptions
Function Table
H = HIGH Logic Level L = LOW Logic Level
Connection Diagrams
(Top View)
Pin One Orientation Diagram
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
Pad Assignments for MicroPak
(Top Thru View)
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation. MIcroPak is a trademark of Fairchild Semiconductor Corporation.
Product
Package Description Supplied AsOrder Package Code
Number Number Top Mark
NC7WZ32K8X MAB08A WZ32 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
NC7WZ32L8X MAC08A N5 Pb-Free 8-Lead MicroPak, 1.6 mm Wide 5k Units on Tape and Reel
Pin Names Description
A
n
, B
n
Inputs
Y
n
Output
Y
= A + B
Input Output
ABY
LLL
LHH
HLH
HHH
Verzeichnis
