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June 1997
NDS332P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
________________________________________________________________________________
Asolute Maximum Ratings T
A
= 25°C unless otherwise noted
Symbol Parameter NDS332P Units
V
DSS
Drain-Source Voltage -20 V
V
GSS
Gate-Source Voltage - Continuous ±8 V
I
D
Drain Current - Continuous (Note 1a) -1 A
- Pulsed -10
P
D
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
0.46
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
NDS332P Rev. E
-1 A, -20 V, R
DS(ON)
= 0.41 Ω @ V
GS
= -2.7 V
R
DS(ON)
= 0.3 Ω @ V
GS
= -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.0V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface Mount
package.
D
S
G
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications such as
notebook computer power management, portable electronics,
and other battery powered circuits where fast high-side
switching, and low in-line power loss are needed in a very small
outline surface mount package.
© 1997 Fairchild Semiconductor Corporation
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