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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5606S
Rev. 8, 11/2011
© Freescale Semiconductor, Inc., 2008–2011. All rights reserved.
MPC5606S
LQFP176 (24 x 24 mm)LQFP144 (20 x 20 mm)
MPC5606S Microcontroller
Data Sheet
• Single issue, 32-bit Power Architecture Book E compliant
CPU core complex (e200z0h)
– Compatible with classic PowerPC instruction set
– Includes variable length encoding (VLE) instruction set
for smaller code size footprint; with the encoding of
mixed 16-bit and 32-bit instructions, it is possible to
achieve significant code size footprint reduction over
conventional Book E compliant code
• On-chip ECC flash memory with flash controller
– Up to 1 MB primary flash—two 512 KB modules with
prefetch buffer and 128-bit data access port
– 64 KB data flash—separate 4 16 KB flash block for
EEPROM emulation with prefetch buffer and 128-bit
data access port
• Up to 48 KB on-chip ECC SRAM with SRAM controller
• Up to 160 KB on-chip non-ECC graphics SRAM with
SRAM controller
• Memory Protection Unit (MPU) with up to 12 region
descriptors and 32-byte region granularity to provide basic
memory access permission
• Interrupt Controller (INTC) with up to 127 peripheral
interrupt sources and eight software interrupts
• 2 Frequency-Modulated Phase-Locked Loops (FMPLLs)
– Primary FMPLL provides a 64 MHz system clock
– Auxiliary FMPLL is available for use as an alternate,
modulated or non-modulated clock source to eMIOS
modules and as alternate clock to the DCU for pixel
clock generation
• Crossbar switch architecture enables concurrent access of
peripherals, flash memory, or RAM from multiple bus
masters (AMBA 2.0 v6 AHB)
• 16-channel Enhanced Direct Memory Access controller
(eDMA) with multiple transfer request sources using a
DMA channel multiplexer
• Boot Assist Module (BAM) supports internal flash
programming via a serial link (FlexCAN or LINFlex)
• Display Control Unit to drive TFT LCD displays
– Includes processing of up to four planes that can be
blended together
– Offers a direct unbuffered hardware bit-blitter of up to
16 software-configurable dynamic layers in order to
drastically minimize graphic memory requirements and
provide fast animations
– Programmable display resolutions are available up to
WVGA
• Parallel Data Interface (PDI) for digital video input
• LCD segment driver module with two software
programmable configurations:
– Up to 40 frontplane drivers and 4 backplane drivers
– Up to 38 frontplane drivers and 6 backplane drivers
• Stepper Motor Controller (SMC) module with high-current
drivers for up to six instrument cluster gauges driven in full
dual H-Bridge configuration including full diagnostics for
short circuit detection
• Stepper motor return-to-zero and stall detection module
• Sound generation and playback utilizing PWM channels
and eDMA; supports monotonic and polyphonic sound
• 24 eMIOS channels providing up to 16 PWM and 24 input
capture / output compare channels
• 10-bit Analog-to-Digital Converter (ADC)
– Maximum conversion time of 1 s
– Up to 16 internal channels, expandable to 23 via external
multiplexing
• Up to 2 Deserial Serial Peripheral Interface (DSPI)
modules for full-duplex, synchronous communications
with external devices (extendable to include up to 8
multiplexed external channels)
• QuadSPI serial flash memory controller supporting single,
dual, and quad modes of operation to interface to external
serial flash memory; QuadSPI can be configured to
function as another DSPI module (MPC5606S only)
• 2 Local Interconnect Network Flexible (LINFlex)
controller modules capable of autonomous message
handling (master), autonomous header handling (slave
