herunterladen
1 Introduction
The MPC57xx family is the first family of devices that include
a new bus for communicating between two devices over a
high speed (320 Mb/s) serial interface called Zipwire. It is
implemented using a Serial Inter-Processor Interface (SIPI)
over an LVDS
1
Fast Asynchronous Serial Transmission
Interface (LFAST). The SIPI module controls the higher level
protocol of the interface, and the LFAST controls the physical
interface.
NOTE
Some devices support two separate
interfaces that are similarly based on the
LFAST and SIPI modules. The first,
discussed in this application note, is the
Zipwire interface that consists of the SIPI
and LFAST modules and is used for
interprocessor communication. Some
devices implement a second separate
interface that can be used as a high-speed
debug interface. This debug Zipwire
interface consists of the LFAST, a reduced
SIPI module that has a very limited
functionality, and a JTAG Master interface
module (JTAGM) that allows access of the
JTAG debug interface through the LFAST
interface.
1. LVDS is Low Voltage Differential Signalling
Freescale Semiconductor
Document Number: AN5134
Application Note
Rev. 0, May 2015
Introduction to the Zipwire
Interface
Inter-Processor Communication with SIPI/LFAST on
the MPC57xx and S32Vxxx families
by: Randy Dees, Hugo Osornio, Steven Becerra, and Ray Marshall
© 2015 Freescale Semiconductor, Inc.
Contents
1 Introduction............................... ............................... 1
2 Zipwire Interface overview.......................................2
2.1 Zipwire SIPI LFAST software
model........................................... ..................4
2.2 Typical Zipwire example
overview........................................................ 5
3 Zipwire examples......................................................6
3.1 Function file locations............. ...................... 6
3.2 Zipwire demo overview.................................7
3.3 LFAST clock settings............. .....................12
3.4 Zipwire pins................................................. 13
3.5 Example Configuration........... .................... 14
4 LFAST configuration.................... ......................... 15
5 Zipwire hardware and layout............. .....................24
A Zipwire driver............................ .............................25
A.1 Overview......................... ............................ 26
A.2 About this Appendix....................................26
A.3 Zipwire Driver API......................................26
B Zipwire connector....................... ............................35
C References...............................................................37
D Revision history...................................................... 37
