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SLVA785–June 2016
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Copyright © 2016, Texas Instruments Incorporated
Picking ESD Diodes for Ultra High-Speed Data Lines
Application Report
SLVA785–June 2016
Picking ESD Diodes for Ultra High-Speed Data Lines
Will Zhou, Jeff Skarzynski
ABSTRACT
This application report addresses three key criteria for selecting an ESD device for protecting high-speed
signals. As the industry continues to trend towards smaller chipset features sizes to address higher speed
data rates, tolerance of transient voltages has continued to shrink as well. Picking the right ESD device
the first time is critical to preventing costly board re-spins during EMC testing. By using the three
techniques discussed in this paper, device selection can be greatly simplified and streamlined.
Contents
1 Introduction ................................................................................................................... 1
2 TLP Analysis ................................................................................................................. 1
3 Eye Diagram Analysis....................................................................................................... 4
4 Layout Considerations ...................................................................................................... 5
5 Conclusion.................................................................................................................... 5
6 References ................................................................................................................... 6
List of Figures
1 TLP Measurement Example................................................................................................ 2
2 Example IC TLP Results.................................................................................................... 3
3 Example IC TLP Results with TPD1E04U04 Superimposed .......................................................... 3
4 USB 3.1 Gen 2 10-Gbps Eye Diagram (Bare Board)................................................................... 4
5 USB 3.1 Gen 2 10-Gbps Eye Diagram (with TPD1E01B04)........................................................... 4
6 Example Layout with 4-Channel Routing Inefficiencies ................................................................ 5
1 Introduction
When designing a system to support high speed interfaces such as USB 3.1 Gen 2, HDMI 2.0,
DisplayPort 1.3, or Thunderbolt, a designer must take into account the entire system in order to meet all
end customer requirements. When selecting a TVS diode device, two important criteria come into account:
does this device’s added capacitance still allow my signals to pass cleanly, and does this device provide
the necessary protection from transient events such as ESD? This paper discusses three techniques that
can be applied to satisfy the two main TVS diode requirements. Those techniques are:
• TLP analysis – to understand the system breaking point, and the right device to protect it
• Eye diagram analysis – to show what effect a TVS diode has on the system eye diagram
• Layout considerations – best practices that can improve ESD performance and signal integrity
2 TLP Analysis
The TLP (Transmission Line Pulse) test is an efficient way to characterize a protection structure’s
performance during ESD events. Since TLP has a similar transient duration as IEC 61000-4-2 ESD events
and regular waveform shapes, it is common to use this test for assessing how well an ESD device clamps
during the IEC strikes. The lower voltage a TLP curve shows for a certain current level, the better it
clamps for ESD, which provides more protection for the sensitive ICs behind it.
