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DS001 June 13, 2008 www.xilinx.com
Product Specification 1
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
This document includes all four modules of the Spartan
®
-II FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS001-1 (v2.8) June 13, 2008
Introduction
•Features
General Overview
Product Availability
User I/O Chart
Ordering Information
Module 2:
Functional Description
DS001-2 (v2.8) June 13, 2008
Architectural Description
- Spartan-II Array
- Input/Output Block
- Configurable Logic Block
-Block RAM
- Clock Distribution: Delay-Locked Loop
- Boundary Scan
Development System
Configuration
- Configuration Timing
Design Considerations
Module 3:
DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
DC Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics
- Power-On Requirements
- DC Input and Output Levels
Switching Characteristics
- Pin-to-Pin Parameters
- IOB Switching Characteristics
- Clock Distribution Characteristics
- DLL Timing Parameters
- CLB Switching Characteristics
- Block RAM Switching Characteristics
- TBUF Switching Characteristics
- JTAG Switching Characteristics
Module 4:
Pinout Tables
DS001-4 (v2.8) June 13, 2008
Pin Definitions
Pinout Tables
IMPORTANT NOTE: This Spartan-II FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
Spartan-II FPGA Family
Data Sheet
DS001 June 13, 2008 Product Specification
R
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XC2S100E-6FGG456C Datenblatt-PDF

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