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Dual, 12-Bit nanoDAC+
with 2 ppm/°C Reference, I
2
C Interface
Data Sheet
AD5697R
Rev. B Document Feedback
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FEATURES
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of full-scale range (FSR)
maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
Low glitch: 0.5 nV-sec
400 kHz I
2
C-compatible serial interface
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Base station power amplifiers
Process controls (programmable logic controller [PLC] I/O cards)
Industrial automation
Data acquisition systems
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD5697R, a member of the nanoDAC+™ family, is a low power,
dual, 12-bit buffered voltage output digital-to-analog converter
(DAC). The device includes a 2.5 V, 2 ppm/°C internal reference
(enabled by default) and a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). The AD5697R operates from
a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design,
and exhibits less than 0.1% FSR gain error and 1.5 mV offset
error performance. The device is available in a 3 mm × 3 mm
LFCSP and a TSSOP package.
The AD5697R also incorporates a power-on reset circuit and a
RSTSEL pin that ensure that the DAC outputs power up to zero
scale or midscale and remain there until a valid write takes
place. It contains a per channel power-down feature that reduces
the current consumption of the device to 4 µA at 3 V while in
power-down mode.
The AD5697R uses a versatile 2-wire serial interface that operates
at clock rates up to 400 kHz and includes a V
LOGIC
pin intended
for 1.8 V/3 V/5 V logic.
Table 1. Dual nanoDAC+ Devices
Interface Reference 16-Bit 12-Bit
SPI Internal AD5689R AD5687R
External AD5689 AD5687
I
2
C Internal AD5697R
PRODUCT HIGHLIGHTS
1. Precision DC Performance.
TUE: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
SCL
V
LOGIC
SDA
A1
A0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
V
OUT
A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
V
REFGND
V
DD
POWER-
DOWN
LOGIC
POWER-ON
RESET
GAIN =
×1/×2
INTERFACE LOGIC
RSTSEL GAIN
LDAC RESET
AD5697R
2.5V
REFERENCE
11253-001
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 9 Seite 20 Seite 27
- ・ Abmessungen des Paketumrisses on Seite 27
- ・ Teilenummerierungssystem on Seite 27
- ・ Blockdiagramm on Seite 1 Seite 18
- ・ Schweißen Temperatur on Seite 8
- ・ Beschreibung der Funktionen on Seite 1 Seite 9 Seite 27
- ・ Technische Daten on Seite 1 Seite 4 Seite 8
- ・ Anwendungsbereich on Seite 1 Seite 26
- ・ Elektrische Spezifikation on Seite 10
