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AM5K2E04, AM5K2E02
SPRS864D –NOVEMBER 2012–REVISED MARCH 2015
AM5K2E0x Multicore ARM KeyStone II System-on-Chip (SoC)
1 AM5K2E0x Features and Description
1.1 Features
1
• Audio/Video Bridging (802.1Qav/D6.0)
• ARM
®
Cortex
®
-A15 MPCore™ CorePac
• QOS Capability
– Up to Four ARM Cortex-A15 Processor Cores at
up to 1.4-GHz
• DSCP Priority Mapping
– 4MB L2 Cache Memory Shared by all Cortex-
• Peripherals
A15 Processor Cores
– Two PCIe Gen2 Controllers with Support for
– Full Implementation of ARMv7-A Architecture
• Two Lanes per Controller
Instruction Set
• Supports Up to 5 GBaud
– 32KB L1 Instruction and Data Caches per Core
– One HyperLink
– AMBA 4.0 AXI Coherency Extension (ACE)
• Supports Connections to Other KeyStone
Master Port, Connected to MSMC (Multicore
Architecture Devices Providing Resource
Shared Memory Controller) for Low Latency
Scalability
Access to SRAM and DDR3
• Supports Up to 50 GBaud
• Multicore Shared Memory Controller (MSMC)
– 10-Gigabit Ethernet (10-GbE) Switch Subsystem
– 2 MB SRAM Memory for ARM CorePac
• Two SGMII/XFI Ports with Wire Rate
– Memory Protection Unit for Both SRAM and
Switching and MACSEC Support
DDR3_EMIF
• IEEE1588 v2 (with Annex D/E/F) Support
• Multicore Navigator
– One 72-Bit DDR3/DDR3L Interface with Speeds
– 8k Multi-Purpose Hardware Queues with Queue
Up to 1600 MTPS in DDR3 Mode
Manager
– EMIF16 Interface
– One Packet-Based DMA Engine for Zero-
– Two USB 2.0/3.0 Controllers
Overhead Transfers
– USIM Interface
• Network Coprocessor
– Two UART Interfaces
– Packet Accelerator Enables Support for
– Three I
2
C Interfaces
• Transport Plane IPsec, GTP-U, SCTP,
– 32 GPIO Pins
PDCP
– Three SPI Interfaces
• L2 User Plane PDCP (RoHC, Air Ciphering)
– One TSIP
• 1 Gbps Wire Speed Throughput at 1.5
• Support 1024 DS0s
MPackets Per Second
• Support 2 Lanes at 32.768/16.3848.192
– Security Accelerator Engine Enables Support for
Mbps Per Lane
• IPSec, SRTP, 3GPP and WiMAX Air
• System Resources
Interface, and SSL/TLS Security
– Three On-Chip PLLs
• ECB, CBC, CTR, F8, A5/3, CCM, GCM,
– SmartReflex Automatic Voltage Scaling
HMAC, CMAC, GMAC, AES, DES, 3DES,
Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
– Semaphore Module
Hash), MD5
– Twelve 64-Bit Timers
• Up to 6.4 Gbps IPSec and 3 Gbps Air
– Five Enhanced Direct Memory Access (EDMA)
Ciphering
Modules
– Ethernet Subsystem
• Commercial Case Temperature:
• Eight SGMII Ports with Wire Rate Switching
– 0ºC to 85ºC
• IEEE1588 v2 (with Annex D/E/F) Support
• Extended Case Temperature:
• 8 Gbps Total Ingress/Egress Ethernet BW
– -40ºC to 100ºC
from Core
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Verzeichnis
- ・ Abmessungen des Paketumrisses on Seite 249
- ・ Markierungsinformationen on Seite 249 Seite 250
- ・ Blockdiagramm on Seite 4 Seite 5 Seite 14 Seite 15 Seite 212
- ・ Technische Daten on Seite 175 Seite 179 Seite 180 Seite 181 Seite 182
- ・ Anwendungsbereich on Seite 2 Seite 230
- ・ Elektrische Spezifikation on Seite 176 Seite 177 Seite 179 Seite 180 Seite 181
