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User's Guide
SCAU035 – July 2009
Low Additive Phase Noise Clock Buffer Evaluation Board
Figure 1. CDCLVP1102 Evaluation Board
Features:
• Easy-to-use evaluation board to fan out low phase noise clocks
• Easy device setup
• Fast configuration
• Control pins configurable through jumpers
• Board powered at +2.5-/+3.3-V
• Single-ended or differential input clocks
• CDCLVP1102 supports two LVPECL outputs; CDCLVP1102EVM supports one LVPECL output
Contents
1 General Description ......................................................................................................... 2
2 Signal Path and Control Circuitry .......................................................................................... 2
3 Getting Started ............................................................................................................... 2
4 Input Clock Selection ........................................................................................................ 3
5 Output Clock .................................................................................................................. 3
6 Schematics and Layout ..................................................................................................... 3
List of Figures
1 CDCLVP1102 Evaluation Board ........................................................................................... 1
2 CDCLVP1102EVM—Schematic ........................................................................................... 4
3 CDCLVP1102EVM—Schematic ........................................................................................... 5
SCAU035 – July 2009 Low Additive Phase Noise Clock Buffer Evaluation Board 1
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