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Maxim > Design Support > Technical Documents > Application Notes > Microcontrollers > APP 91
Keywords: DS80C320, DS80C310, ALE, address latch enable, ALE noise, high-speed microcontroller,
Dallas Semiconductor, multiplexed address/data
APPLICATION NOTE 91
Microcontroller Design Guidelines for Reducing
ALE Signal Noise
By: Kevin Self
May 01, 2001
Abstract: When using a Dallas Semiconductor high-speed microcontroller with external memory, noise
from P0 switching could couple to ALE. With careful board layout and a good understanding of induced
noise on a multiplexed address/data bus, these problems can be minimized. This application note looks
at the DS80C320 high-speed microcontroller when accessing external memory.
Overview
The 8051 architecture allows for external program and data access through the use of Port 0 and Port 2
as an external memory interface. The 8051 architecture multiplexes the data and LSB of address on Port
0, requiring a 74373 latch for demultiplexing. This means that Port 0 will be directly connected to at least
two devices. More devices may be placed on the bus if an external data SRAM or memory-mapped
peripherals are used.
Because Port 0 must switch quickly between address and data, it requires strong current drive
characteristics. Unfortunately, the high instantaneous current requirements of quickly switching all the
pins of Port 0 can induce noise on the ALE signal. In some instances, this noise can interfere with
program and data accesses by causing the external hardware to latch an incorrect address. This is a
relatively rare occurrence, and most designers will not encounter it. The magnitude of this problem is
directly related to several issues associated with both the system and software. Devices which do not
access external memory via Port 0 and Port 2 will not experience this problem.
This application note will discuss ways the system designer can reduce the effects of Port 0 switching on
device operation. It is applicable to any ROMless 8051 microcontroller which accesses external memory
via Port 0 and Port 2, including the DS80C310 and DS80C320. It is also applicable to any microcontroller
with internal program memory that accesses external memory.
ALE Noise Generation
Under certain system conditions, noise induced on ALE can cause an incorrect LSB address to be
latched when using the multiplexed address/data bus. The noise, as seen in Figure 1, is generated by
the highspeed switching of Port 0 when the processor stops driving a memory address and begins
driving data during a MOVX write. The noise pulse can, under the right conditions, rise above the V
IH
input threshold of TTL, LS, FS and HCT logic. In this case, the 74373 latch may be falsely triggered,
latching an incorrect address and disturb the LSB address of the MOVX write.
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