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ISL8120EVAL3Z
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ISL8120EVAL3Z Benutzerreferenzhandbuch - Intersil

  • Hersteller:
    Intersil
  • Kategorie:
    Microprocessor Primary Platform
  • Fallpaket
    Board
  • Beschreibung:
    ISL8120 EVALUATION BOARD 3 - RoHS COMPLIANT - QFN -1 Con HT SUSA CODE:8534000040
Aktualisierte Uhrzeit: 2025-04-25 20:30:14 (UTC+8)

ISL8120EVAL3Z Benutzerreferenzhandbuch

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Application Note 1528
ISL8120EVAL3Z Evaluation Board Setup Procedure
ISL8120EVAL3Z Evaluation Board
The ISL8120 integrates two voltage-mode
synchronous buck PWM controllers. It can be used
either for dual independent outputs or a 2-phase
single-output regulator.
The ISL8120EVAL3Z evaluation board is for
performance demo of the dual independent outputs
and DDR applications.
The ISL8120EVAL4Z evaluation board is used for
performance demo of 2/n-phase single-output
applications. Application note “ISL8120EVAL4Z
Evaluation Board Setup Procedure” will soon be available
for the ISL8120EVAL4Z board.
Recommended Equipment
0V to 22V power supply with at least 20A source
current capability, battery, or notebook AC adapter.
Two Electronic Loads capable of sinking current up to
30A
Digital multi-meters (DMMs).
100MHz quad-trace oscilloscope.
Circuits Description
J1 and J2 are the input power terminals.
Two input electrolytic caps are used to handle the input
current ripples.
Two upper and two lower Renesas “speed“series LFPAK
MOSFETs are used for each channel. Q1 and Q2 are
footprint options for low current applications where a
SO8 package integrating dual MOSFET can be used.
320nH PULSE surface mount inductors are used for each
channel. Under the 500kHz setup, the inductor current
peak to peak ripple is 7.5A at 12V input.
Two SANYO POSCAP 2R5TPF470M7L (7mΩ) are used as
output E-caps for each channel. Also, through hole
electrolytic cap footprints C123 ~ C126 are available for
the user to evaluate different output caps.
J7, J8, J9 and J10 are output lugs for load connections.
TP19, TP26, TP28 and TP31 are remote sense posts.
These pins can be used to monitor and evaluate the
system voltage regulations. If the user want to use these
test posts for remote sense, the R109, R120, R155 and
R161 need to be changed to higher values, such as 10Ω.
Also, the related voltage sense divider needs to be
increased to a higher resistance, such as 1k.
Q26, Q27, R126, R156, R122, R131, R151, R153 are
circuit footprint options to add a on-board transient load
to the regulator. Use a signal generator to apply a clock
signal at TP22 (TP30) to generate step up and step down
transient load. Make sure that the duty cycle of the clock
FIGURE 1. ISL8120EVAL3Z EVALUATION BOARD
February 11, 2010
AN1528.0

ISL8120EVAL3Z Datenblatt-PDF

ISL8120EVAL3Z Datenblatt PDF
Intersil
38 Seiten, 1192 KB
ISL8120EVAL3Z Benutzerreferenzhandbuch
Intersil
11 Seiten, 817 KB

ISL8120EVAL3 Datenblatt-PDF

ISL8120EVAL3Z
Datenblatt PDF
Intersil
ISL8120 EVALUATION BOARD 3 - RoHS COMPLIANT - QFN -1 Con HT SUSA CODE:8534000040
ISL8120EVAL3Z
Datenblatt PDF
Renesas Electronics
ISL8120 EVALUATION BOARD 3 - RoHS COMPLIANT - QFN -1 Con HT SUSA CODE:8534000040
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