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www.latticesemi.com 1 tn1257_01.3
October 2013 Technical Note TN1257
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
This document provides general PCB layout guidance for Lattice QFP (Quad Flat Package) and QFN (Quad Flat
No Lead) products. Table 1 below lists the common nomenclature for different types of packages. As it is antici-
pated that users may have specific PCB design rules and requirements, the recommendations made herein should
be considered as reference guidelines only.
When designing a PCB for a QFN or QFP package, the following primary factors can affect the successful package
mounting on the board:
Perimeter Land Pad and Trace Design
Stencil design
Type of vias
Board thickness
Lead finish on the package
Surface finish on the board
Type of solder paste
Reflow profile
Table 1. Leaded Package Types
Package Type Description
QFN Quad Flat No Lead. Plastic package with flat lead frame base coplanar along its bottom side.
DR-QFN Dual Row-Quad Flat No Lead. QFN package that has two row staggered contacts.
QFP Quad Flat Package. Plastic package with “gull wing” leads extending from four sides of the body.
PQFP Plastic Quad Flat Package. QFP with body thickness from 2.0mm and above.
TQFP Thin Quad Flat Package. QFP with thin body profile typical at 1.40mm and 1.0mm.
PCB Layout Recommendations
for Leaded Packages
Verzeichnis

LC5512MV-75Q208I Datenblatt-PDF

LC5512MV-75Q208I Datenblatt PDF
Lattice Semiconductor
92 Seiten, 601 KB
LC5512MV-75Q208I Benutzerreferenzhandbuch
Lattice Semiconductor
13 Seiten, 2121 KB
LC5512MV-75Q208I Programmierhandbuch
Lattice Semiconductor
99 Seiten, 1438 KB
LC5512MV-75Q208I Anderes Datenblatt
Lattice Semiconductor
10 Seiten, 760 KB
LC5512MV-75Q208I Diagramme zeichnen
Lattice Semiconductor
124 Seiten, 14507 KB

LC5512MV75Q208 Datenblatt-PDF

LC5512MV-75Q208C Datenblatt PDF
Lattice Semiconductor
CPLD ispXPLD 5000mV Family 150K Gates 512 Macro Cells 150MHz 3.3V 208Pin PQFP
LC5512MV-75Q208I Datenblatt PDF
Lattice Semiconductor
CPLD ispXPLD 5000mV Family 150K Gates 512 Macro Cells 150MHz 3.3V 208Pin PQFP
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