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User's Guide
SNVA351B–March 2009–Revised April 2013
AN-1859 LP38512MR-ADJ Evaluation Board
1 Introduction
This board is designed to allow the evaluation of the LP38512MR-ADJ Voltage Regulator. Each board is
assembled and tested in the factory. This evaluation board has the PSOP-8 package mounted, and the
output voltage is set to 1.20V.
2 General Description
The LP38512MR-ADJ is an adjustable LDO linear regulator capable of supplying up to 1.5A of output
current, and incorporates an Enable function.
The device has been designed to work with 10 µF input and output ceramic capacitors. Footprints areas
for C
IN
and C
OUT
will allow for a variety of sizes.
3 Operation
The input voltage, applied between V
IN
and GND, should be at least 2.25V, or at least 500 mV greater
than V
OUT
, whichever value is larger. The input voltage should be no greater than 5.5V, which is the high
end of the Operating Rating voltage.
Loads can be connected to V
OUT
with reference to GND.
V
OUT
and V
IN
test points are provided on the board to allow accurate measurements directly onto the input
and output pins of the device, eliminating any voltage drop on the PCB traces or connecting wires to the
load.
4 Setting V
OUT
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
V
OUT
= V
ADJ
× (1 + (R1 / R2)) (1)
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than
1.00 kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the F
Z
pole
set by R1 and C
FF
.
( (R1 × R2) / (R1 + R2) ) ≤ 1.00 kΩ (2)
Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for C
FF
, for a range of V
OUT
values. Other values of R1, R2, and C
FF
are available that will
give similar results.
Refer to AN-1378 Method for Calculating Output Voltage Tolerances in Adjustable Regulators Application
Report (SNVA112) for additional information on how resistor tolerances affect the calculated V
OUT
value.
The LP38512MR-ADJ Evaluation board is assembled with a 1.40 kΩ ±1% resistor for R1, and a
1.00 kΩ ±1% resistor for R2. This sets V
OUT
to 1.20V.
V
OUT
= 500 mV × (1 + (1.40 kΩ / 1.00 kΩ ) ) (3)
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1
SNVA351B–March 2009–Revised April 2013 AN-1859 LP38512MR-ADJ Evaluation Board
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Verzeichnis
- ・ Blockdiagramm on Seite 4
- ・ Beschreibung der Funktionen on Seite 1
- ・ Anwendungsbereich on Seite 8
