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© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 4
1 Publication Order Number:
MC100LVEL34/D
MC100LVEL34
3.3V ECL ÷2, ÷4, ÷8 Clock
Generation Chip
Description
The MC100LVEL34 is a low skew ÷ 2, ÷ 4, ÷ 8 clock generation
chip designed explicitly for low skew clock generation applications.
The internal dividers are synchronous to each other, therefore, the
common output edges are all precisely aligned. The V
BB
pin, an
internally generated voltage supply, is available to this device only.
For single−ended input conditions, the unused differential input is
connected to V
BB
as a switching reference voltage. V
BB
may also
rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
BB
should be left open.
The common enable (EN
) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon start−up, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple LVEL34s in a system.
Features
• 50 ps Typical Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 1.5 GHz Toggle Frequency
• The 100 Series Contains Temperature Compensation.
• PECL Mode Operating Range:
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
• NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= −3.0 V to −3.8 V
• Open Input Default State
• LVDS Input Compatible
• These are Pb−Free Devices
SO−16
D SUFFIX
CASE 751B
1
16
MARKING
DIAGRAMS*
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
G or G = Pb−Free Package
1
16
100LVEL34G
AWLYWW
1
16
TSSOP−16
DT SUFFIX
CASE 948F
VL34
ALYW G
G
100
1
16
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 2
- ・ Abmessungen des Paketumrisses on Seite 8 Seite 9
- ・ Paket-Footprint-Pad-Layout on Seite 8 Seite 9
- ・ Teilenummerierungssystem on Seite 1 Seite 7 Seite 9
- ・ Markierungsinformationen on Seite 1 Seite 7 Seite 9
- ・ Typisches Anwendungsschaltbild on Seite 2
- ・ Technische Daten on Seite 7
- ・ Elektrische Spezifikation on Seite 4
- ・ Teilenummernliste on Seite 3
