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© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 1
1 Publication Order Number:
EVBUM2295/D
NB3L208KMNGEVB
NB3L208K
Evaluation Board
User's Manual
Introduction
The NB3L208K is a differential 1:8 Clock fanout buffer
with High-speed Current Steering Logic (HCSL) outputs.
Inputs can directly accept differential LVPECL, LVDS and
HCSL signals. Single-ended LVPECL, HCSL, LVCMOS,
or LVTTL levels are accepted with a proper external V
TH
reference supply. These signals will be translated to HCSL
and eight identical copies of Clock will be distributed,
operating up to 350 MHz.
This manual should be used in conjunction with the device
datasheet, which contains full technical details on the device
specifications and operation.
This evaluation board manual contains:
• Information on the NB3L208K Evaluation Board
• Block Diagram and Board Schematic
• Assembly Instructions
• Test and Measurement Setup Procedures
• Bill of Materials
Figure 1. NB3L208KMNGEVB Top and Bottom View
Top View Bottom View
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EVAL BOARD USER’S MANUAL
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