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NCP1082DER2G Benutzerreferenzhandbuch

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© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 1
1 Publication Order Number:
AND9133/D
AND9133/D
Circuit Design and PCB
Layout Guidelines for
Designs Using the NCP108x
Introduction
The NCP108x integrates a Power-over-Ethernet interface
with a DC-DC controller, reducing the BOM for
a Power-over-Ethernet implementation. However, DC-DC
convertor design is not always easy, especially considering
the many EMC and EMI pitfalls. Regulatory testing often
reveals that a convertor design radiates more than is allowed
by regulations. In this document, we will give some
guidelines on how to build a power supply that can pass these
tests.
Schematic Design and Component Selection
Designing a PCB that will pass regulatory testing requires
that attention for EMC issues is not an afterthought, but is
present right from the beginning at the start of the circuit
design. Often, not taking small measures early on in the
design will result in big and costly patches later on, such as
ferrite bead clamps on the cables which could have been
avoided by placing much smaller ferrite beads on the PCB.
Here are a couple of things to do while drawing the
schematic and selecting the components:
On the input connector, use a Bob-Smith Termination
Network to properly terminate the Ethernet connection.
Use input common-mode chokes.
Use a shielded RJ-45 connector. It is possible to use an
integrated connector, which can include common-mode
chokes, the Ethernet transformer and the Bob-Smith
network. This is preferable, as it will result in a more
compact design.
Use an LC filter on the input and output of the DC/DC
convertor.
Allow for snubbers on all switching components. When
designing a flyback convertor this absolutely required,
but even on other topologies this can be beneficial.
Limit the switching edge rise time by inserting a small
resistor before the gate of the switching transistor.
Place a small (1 nF or 2.2 nF) bridge capacitor across
the isolation boundary. This capacitor should be rated at
least 2 kV.
Use ferrite beads on input and output lines of the
DC/DC convertor. When not required, these beads can
be replaced by 0 W resistors.
Foresee a possibility for a shielding box over the
DC/DC convertor.
Figure 1. Bob Smith Termination for
Power-over-Ethernet Circuits
PoE1
PoE2
PoE3
PoE4
1 nF, 2 kV
12 nF,
100 V
75 W
PCB Layout and Component Placement
The most critical time for avoiding EMC issues in the
product design is during the PCB layout. Great care must be
taken to avoid current loops and radiating stubs. Below is
a list of attention points that will minimize the risk of issues
later on:
If possible, use a 4 layer PCB. This will allow big
ground and power planes, and will allow return currents
to flow freely, resulting in compacter current loops.
Use copper ground planes and surround the outside
layers in a copper ground flood.
Tie ground flood and planes together with vias at
regular intervals.
Ground and power planes should only be present near
areas where these planes are used. Output ground and
power layers should not be present under the Ethernet
input or the converter primary side.
At the input, use the Bob-Smith Termination virtual
ground as the ground shield.
APPLICATION NOTE
www.onsemi.com
Verzeichnis

NCP1082DER2G Datenblatt-PDF

NCP1082DER2G Datenblatt PDF
ON Semiconductor
17 Seiten, 215 KB
NCP1082DER2G Benutzerreferenzhandbuch
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2 Seiten, 61 KB
NCP1082DER2G Anderes Datenblatt
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17 Seiten, 845 KB
NCP1082DER2G Diagramme zeichnen
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NCP1082DER2 Datenblatt-PDF

NCP1082DER2G
Datenblatt PDF
ON Semiconductor
Integrated PoE-PD and DC-DC Converter Controller 20Pin TSSOP EP T/R
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