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OMAP3525-HiRel, OMAP3530-HiRel
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SPRS599D–JUNE 2009–REVISED AUGUST 2010
OMAP3525-HiRel and OMAP3530-HiRel Applications Processor
Check for Samples: OMAP3525-HiRel, OMAP3530-HiRel
1 OMAP3525-HiRel and OMAP3530-HiRel Applications Processor
1.1 Features
1234
– Instruction Packing Reduces Code Size
• OMAP325 and OMAP3530 Applications
Processor: – All Instructions Conditional
– OMAP™ 3 Architecture – Additional C64x+™ Enhancements
– MPU Subsystem • Protected Mode Operation
• Up to 600-MHz ARM Cortex™-A8 Core • Exceptions Support for Error Detection
and Program Redirection
• NEON™ SIMD Coprocessor
• Hardware Support for Modulo Loop
– High Performance Image, Video, Audio
Operation
(IVA2.2™) Accelerator Subsystem
• C64x+ L1/L2 Memory Architecture
• Up to 520-MHz TMS320C64x+™ DSP Core
– 32K-Byte L1P Program RAM/Cache (Direct
• Enhanced Direct Memory Access (EDMA)
Mapped)
Controller (128 Independent Channels)
– 80K-Byte L1D Data RAM/Cache (2-Way
• Video Hardware Accelerators
Set-Associative)
– POWERVR SGX™ Graphics Accelerator
– 64K-Byte L2 Unified Mapped RAM/Cache
(OMAP3530 Device Only)
(4-Way Set-Associative)
• Tile Based Architecture Delivering up to
– 32K-Byte L2 Shared SRAM and 16K-Byte L2
10 MPoly/sec
ROM
• Universal Scalable Shader Engine:
• C64x+ Instruction Set Features
Multi-threaded Engine Incorporating Pixel
and Vertex Shader Functionality – Byte-Addressable (8-/16-/32-/64-Bit Data)
• Industry Standard API Support: – 8-Bit Overflow Protection
OpenGLES 1.1 and 2.0, OpenVG1.0
– Bit-Field Extract, Set, Clear
• Fine Grained Task Switching, Load
– Normalization, Saturation. Bit-Counting
Balancing, and Power Management
– Compact 16-Bit Instructions
• Programmable High Quality Image
– Additional Instructions to Support Complex
Anti-Aliasing
Multiplies
– Fully Software-Compatible With C64x and
• ARM Cortex™-A8 Core
ARM9™
– ARMv7 Architecture
– Commercial and Extended Temperature
• Trust Zone®
Grades
• Thumb®-2
• Advanced Very-Long-Instruction-Word (VLIW)
• MMU Enhancements
TMS320C64x+™ DSP Core
– In-Order, Dual-Issue, Superscalar
– Eight Highly Independent Functional Units
Microprocessor Core
• +Six ALUs (32-/40-Bit), Each Supports
– NEON™ Multimedia Architecture
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
– Over 2x Performance of ARMv6 SIMD
Arithmetic per Clock Cycle
– Supports Both Integer and Floating Point
• Two Multipliers Support Four 16 x 16-Bit
SIMD
Multiplies (32-Bit Results) per Clock
– Jazelle® RCT Execution Environment
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Architecture
Results) per Clock Cycle
– Dynamic Branch Prediction with Branch
– Load-Store Architecture With Non-Aligned
Target Address Cache, Global History
Support
Buffer, and 8-Entry Return Stack
– 64 32-Bit General-Purpose Registers
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2POWERVR SGX is a trademark of Imagination Technologies Ltd.
3OMAP is a trademark of Texas Instruments.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 5 Seite 13
- ・ Abmessungen des Paketumrisses on Seite 258
- ・ Markierungsinformationen on Seite 258
- ・ Blockdiagramm on Seite 7 Seite 176 Seite 177 Seite 178
- ・ Beschreibung der Funktionen on Seite 195
- ・ Technische Daten on Seite 120 Seite 133 Seite 134 Seite 135 Seite 136
- ・ Anwendungsbereich on Seite 1 Seite 2 Seite 3 Seite 4 Seite 5
- ・ Elektrische Spezifikation on Seite 118 Seite 119 Seite 120 Seite 121 Seite 122
