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SGUS036B − JULY 2003 − REVISED OCTOBER 2003
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−55°C to 125°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree
†
D High-Performance Static CMOS Technology
− 25-ns Instruction Cycle Time (40 MHz)
− 40-MIPS Performance
− Low-Power 3.3-V Design
D Based on TMS320C2xx DSP CPU Core
− Code-Compatible With F243/F241/C242
− Instruction Set and Module Compatible
With F240/C240
D On-Chip Memory
− 32K Words x 16 Bits of Flash EEPROM
(4 Sectors) or ROM
− Programmable “Code-Security” Feature
for the On-Chip Flash/ROM
− Up to 2.5K Words x 16 Bits of
Data/Program RAM
− 544 Words of Dual-Access RAM
− 2K Words of Single-Access RAM
D Boot ROM
− SCI/SPI Bootloader
D External Memory Interface
− 192K Words x 16 Bits of Total Memory:
64K Program, 64K Data, 64K I/O
D Watchdog (WD) Timer Module
D 10-Bit Analog-to-Digital Converter (ADC)
− 8 or 16 Multiplexed Input Channels
− 375 ns or 500 ns MIN Conversion Time
− Selectable Twin 8-State Sequencers
Triggered by Two Event Managers
D Controller Area Network (CAN) 2.0B Module
D Serial Communications Interface (SCI)
D 16-Bit Serial Peripheral Interface (SPI)
D Two Event-Manager (EV) Modules
(EVA and EVB), Each Includes:
− Two 16-Bit General-Purpose Timers
− Eight 16-Bit Pulse-Width Modulation
(PWM) Channels Which Enable:
− Three-Phase Inverter Control
− Center- or Edge-Alignment of PWM
Channels
− Emergency PWM Channel Shutdown
With External PDPINTx
Pin
− Programmable Deadband (Deadtime)
Prevents Shoot-Through Faults
− Three Capture Units for Time-Stamping
of External Events
− Input Qualifier for Select Pins
− On-Chip Position Encoder Interface
Circuitry
− Synchronized A-to-D Conversion
− Designed for AC Induction, BLDC,
Switched Reluctance, and Stepper Motor
Control
− Applicable for Multiple Motor and/or
Converter Control
D Phase-Locked-Loop (PLL)-Based Clock
Generation
D 40 Individually Programmable, Multiplexed
General-Purpose Input/Output (GPIO) Pins
D Five External Interrupts (Power Drive
Protection, Reset, Two Maskable Interrupts)
D Power Management:
− Three Power-Down Modes
− Ability to Power Down Each Peripheral
Independently
D Real-Time JTAG-Compliant Scan-Based
Emulation, IEEE Standard 1149.1
‡
(JTAG)
D Development Tools Include:
− Texas Instruments (TI) ANSI C Compiler,
Assembler/Linker, and Code Composer
Studio Debugger
− Evaluation Modules
− Scan-Based Self-Emulation (XDS510)
− Broad Third-Party Digital Motor Control
Support
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio and XDS510 are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
†
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
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