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Feature Summary
• Small area, high clock frequency.
• 32-bit load/store AVR32A RISC architecture.
• 15 general-purpose 32-bit registers.
• 32-bit Stack Pointer, Program Counter and Link Register reside in register file.
• Fully orthogonal instruction set.
• Pipelined architecture allows one instruction per clock cycle for most instructions.
• Byte, half-word, word and double word memory access.
• Fast interrupts and multiple interrupt priority levels.
• Privileged and unprivileged modes enabling efficient and secure Operating Systems.
• Optional MPU allows for operating systems with memory protection.
• Innovative instruction set together with variable instruction length ensuring industry
leading code density.
• DSP extention with saturating arithmetic, and a wide variety of multiply instructions.
• Memory Read-Modify-Write instructions.
• Optional advanced On-Chip Debug system.
• FlashVault™ support through Secure state for executing trusted code alongside
nontrusted code on the same CPU.
• Optional floating-point hardware.
32002F–03/2010
AVR32UC
Technical
Reference
Manual
Verzeichnis
