herunterladen
TMS320C5505
www.ti.com
SPRS660F –AUGUST 2010–REVISED SEPTEMBER 2013
TMS320C5505 Fixed-Point Digital Signal Processor
Check for Samples: TMS320C5505
1 Fixed-Point Digital Signal Processor
1.1 Features
12
• High-Performance, Low-Power, TMS320C55x™ • Universal Asynchronous Receiver/Transmitter
Fixed-Point Digital Signal Processor (UART)
– 16.67-, 13.33-, 10-, 8.33-, 6.66-ns Instruction • Serial-Port Interface (SPI) With Four Chip-
Cycle Time Selects
– 60-, 75-, 100-, 120-, 150-MHz Clock Rate • Master/Slave Inter-Integrated Circuit (I
2
C Bus™)
– One/Two Instructions Executed per Cycle • Four Inter-IC Sound (I
2
S Bus™) for Data
Transport
– Dual Multipliers [Up to 200, 240, or 300
Million Multiply-Accumulates per Second • Device USB Port With Integrated 2.0 High-
(MMACS)] Speed PHY that Supports:
– Two Arithmetic/Logic Units (ALUs) – USB 2.0 Full- and High-Speed Device
– Three Internal Data/Operand Read Buses • LCD Bridge With Asynchronous Interface
and Two Internal Data/Operand Write Buses
• Tightly-Coupled FFT Hardware Accelerator
– Software-Compatible With C55x Devices
• 10-Bit 4-Input Successive Approximation (SAR)
– Industrial Temperature Devices Available ADC
• 320K Bytes Zero-Wait State On-Chip RAM, • Real-Time Clock (RTC) With Crystal Input, With
Composed of: Separate Clock Domain and Power Supply
– 64K Bytes of Dual-Access RAM (DARAM), • Four Core Isolated Power Supply Domains:
8 Blocks of 4K x 16-Bit Analog, RTC, CPU and Peripherals, and USB
– 256K Bytes of Single-Access RAM (SARAM), • Four I/O Isolated Power Supply Domains: RTC
32 Blocks of 4K x 16-Bit I/O, EMIF I/O, USB PHY, and DV
DDIO
• 128K Bytes of Zero Wait-State On-Chip ROM • One integrated LDO (ANA_LDO) to power DSP
(4 Blocks of 16K x 16-Bit) PLL (V
DDA_PLL
) and 10-bit SAR ADC (V
DDA_ANA
)
• 4M x 16-Bit Maximum Addressable External • Low-Power S/W Programmable Phase-Locked
Memory Space (SDRAM/mSDRAM) Loop (PLL) Clock Generator
• 16-/8-Bit External Memory Interface (EMIF) with • On-Chip ROM Bootloader (RBL) to Boot From
Glueless Interface to: NAND Flash, NOR Flash, SPI EEPROM, SPI
Serial Flash or I2C EEPROM
– 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
• IEEE-1149.1 (JTAG)
– 8-/16-Bit NOR Flash
Boundary-Scan-Compatible
– Asynchronous Static RAM (SRAM)
• Up to 26 General-Purpose I/O (GPIO) Pins
– 16-bit SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and
(Multiplexed With Other Device Functions)
3.3-V)
• 196-Terminal Pb-Free Plastic BGA (Ball Grid
• Direct Memory Access (DMA) Controller
Array) (ZCH Suffix)
– Four DMA With 4 Channels Each (16-
• 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V,
Channels Total)
or 3.3-V I/Os
• Three 32-Bit General-Purpose Timers
• 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V,
– One Selectable as a Watchdog and/or GP
or 3.3-V I/Os
• Two MultiMedia Card/Secure Digital (MMC/SD)
• 1.4-V Core (150 MHz), 1.8-V, 2.5-V, 2.75-V or 3.3-
Interfaces
V I/Os
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2010–2013, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 15 Seite 56 Seite 59
- ・ Abmessungen des Paketumrisses on Seite 154
- ・ Markierungsinformationen on Seite 154
- ・ Blockdiagramm on Seite 4
- ・ Typisches Anwendungsschaltbild on Seite 133
- ・ Beschreibung der Funktionen on Seite 56
- ・ Technische Daten on Seite 12 Seite 65 Seite 70 Seite 71 Seite 72
- ・ Anwendungsbereich on Seite 2
- ・ Elektrische Spezifikation on Seite 12 Seite 38 Seite 43 Seite 63 Seite 67
