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1 TMS320C6421 Fixed-Point Digital Signal Processor
1.1 Features
TMS320C6421
Fixed-Point Digital Signal Processor
www.ti.com
SPRS346D – JANUARY 2007 – REVISED JUNE 2008
• High-Performance Digital Signal Processor
(C6421)
– 2.5-, 2.-, 1.67-,1.43- ns Instruction Cycle
• C64x+ L1/L2 Memory Architecture
Time
– 128K-Bit (16K-Byte) L1P Program
– 400-, 500-, 600-, 700-MHz C64x+™ Clock
RAM/Cache [Flexible Allocation]
Rate
– 384K-Bit (48K-Byte) L1D Data RAM/Cache
– Eight 32-Bit C64x+ Instructions/Cycle
[Flexible Allocation]
– 3200, 4000, 4800, 5600 MIPS
– 512K-Bit (64K-Byte) L2 Unified Mapped
– Fully Software-Compatible With C64x
RAM/Cache [Flexible Allocation]
– Commercial and Automotive (Q or S suffix)
• Endianess: Supports Both Little Endian and
Grades
Big Endian
– Low-Power Device (L suffix)
• External Memory Interfaces (EMIFs)
• VelociTI.2™ Extensions to VelociTI™
– 16-Bit DDR2 SDRAM Memory Controller
Advanced Very-Long-Instruction-Word (VLIW)
With 128M-Byte Address Space (1.8-V I/O)
TMS320C64x+™ DSP Core
• Supports up to 266-MHz (data rate) bus
– Eight Highly Independent Functional Units
and interfaces to DDR2-400 SDRAM
With VelociTI.2 Extensions:
– Asynchronous 8-Bit-Wide EMIF (EMIFA)
• Six ALUs (32-/40-Bit), Each Supports
With up to 64M-Byte Address Reach
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
• Flash Memory Interfaces
Arithmetic per Clock Cycle
– NOR (8-Bit-Wide Data)
• Two Multipliers Support Four 16 x 16-Bit
– NAND (8-Bit-Wide Data)
Multiplies (32-Bit Results) per Clock
• Enhanced Direct-Memory-Access (EDMA)
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Controller (64 Independent Channels)
Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
• Two 64-Bit General-Purpose Timers (Each
Support
Configurable as Two 32-Bit Timers)
– 64 32-Bit General-Purpose Registers
• One 64-Bit Watch Dog Timer
– Instruction Packing Reduces Code Size
• One UART With RTS and CTS Flow Control
– All Instructions Conditional
• Master/Slave Inter-Integrated Circuit
– Additional C64x+™ Enhancements
(I
2
C Bus™)
• Protected Mode Operation
• Multichannel Buffered Serial Port (McBSP0)
• Exceptions Support for Error Detection
– I2S and TDM
and Program Redirection
– AC97 Audio Codec Interface
• Hardware Support for Modulo Loop
– SPI
Auto-Focus Module Operation
– Standard Voice Codec Interface (AIC12)
• C64x+ Instruction Set Features
– Telecom Interfaces – ST-Bus, H-100
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 128 Channel Mode
– 8-Bit Overflow Protection
• Multichannel Audio Serial Port (McASP0)
– Bit-Field Extract, Set, Clear
– Four Serializers and SPDIF (DIT) Mode
– Normalization, Saturation, Bit-Counting
– VelociTI.2 Increased Orthogonality • 16-Bit Host-Port Interface (HPI)
– C64x+ Extensions
• 10/100 Mb/s Ethernet MAC (EMAC)
• Compact 16-bit Instructions
– IEEE 802.3 Compliant
• Additional Instructions to Support
– Supports Multiple Media Independent
Complex Multiplies
Interfaces (MII, RMII)
– Management Data I/O (MDIO) Module
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 16 Seite 29 Seite 33 Seite 74 Seite 75
- ・ Abmessungen des Paketumrisses on Seite 218
- ・ Markierungsinformationen on Seite 218 Seite 219
- ・ Blockdiagramm on Seite 4 Seite 107 Seite 108 Seite 117 Seite 118
- ・ Technische Daten on Seite 109 Seite 113 Seite 114 Seite 115 Seite 116
- ・ Anwendungsbereich on Seite 2 Seite 110
- ・ Elektrische Spezifikation on Seite 106 Seite 111 Seite 112 Seite 113 Seite 114
