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TMS320C6746
SPRS591E –NOVEMBER 2009–REVISED MARCH 2014
TMS320C6746™ Fixed- and Floating-Point DSP
1 TMS320C6746 Fixed- and Floating-Point DSP
1.1 Features
1
– 2 SP x DP → DP Every Three Clocks
• 375- and 456-MHz C674x Fixed- and Floating-
Point VLIW DSP
– 2 DP x DP → DP Every Four Clocks
• C674x Instruction Set Features
• Fixed-Point Multiply Supports Two 32 x 32-
Bit Multiplies, Four 16 x 16-Bit Multiplies, or
– Superset of the C67x+ and C64x+ ISAs
Eight 8 x 8-Bit Multiplies per Clock Cycle,
– Up to 3648 MIPS and 2746 MFLOPS
and Complex Multiples
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
– Instruction Packing Reduces Code Size
– 8-Bit Overflow Protection
– All Instructions Conditional
– Bit-Field Extract, Set, Clear
– Hardware Support for Modulo Loop Operation
– Normalization, Saturation, Bit-Counting
– Protected Mode Operation
– Compact 16-Bit Instructions
– Exceptions Support for Error Detection and
• C674x Two-Level Cache Memory Architecture
Program Redirection
– 32KB of L1P Program RAM/Cache
• Software Support
– 32KB of L1D Data RAM/Cache
– TI DSP BIOS™
– 256KB of L2 Unified Mapped RAM/Cache
– Chip Support Library and DSP Library
– Flexible RAM/Cache Partition (L1 and L2)
• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and
• Enhanced Direct Memory Access Controller 3
DDR2 Interfaces)
(EDMA3):
• Two External Memory Interfaces:
– 2 Channel Controllers
– EMIFA
– 3 Transfer Controllers
• NOR (8- or 16-Bit-Wide Data)
– 64 Independent DMA Channels
• NAND (8- or 16-Bit-Wide Data)
– 16 Quick DMA Channels
• 16-Bit SDRAM with 128-MB Address Space
– Programmable Transfer Burst Size
– DDR2/Mobile DDR Memory Controller with one
• TMS320C674x Floating-Point VLIW DSP Core
of the following:
– Load-Store Architecture with Nonaligned
• 16-Bit DDR2 SDRAM with 256-MB Address
Support
Space
– 64 General-Purpose Registers (32-Bit)
• 16-Bit mDDR SDRAM with 256-MB Address
– Six ALU (32- and 40-Bit) Functional Units
Space
• Supports 32-Bit Integer, SP (IEEE Single
• Three Configurable 16550-Type UART Modules:
Precision/32-Bit) and DP (IEEE Double
– With Modem Control Signals
Precision/64-Bit) Floating Point
– 16-Byte FIFO
• Supports up to Four SP Additions Per Clock,
– 16x or 13x Oversampling Option
Four DP Additions Every Two Clocks
• Two Serial Peripheral Interfaces (SPIs) Each with
• Supports up to Two Floating-Point (SP or
Multiple Chip Selects
DP) Reciprocal Approximation (RCPxP) and
• Two Multimedia Card (MMC)/Secure Digital (SD)
Square-Root Reciprocal Approximation
Card Interfaces with Secure Data I/O (SDIO)
(RSQRxP) Operations Per Cycle
Interfaces
– Two Multiply Functional Units:
• Two Master and Slave Inter-Integrated Circuits
• Mixed-Precision IEEE Floating-Point Multiply
( I
2
C Bus™)
Supported up to:
• One Host-Port Interface (HPI) with 16-Bit-Wide
– 2 SP x SP → SP Per Clock
Muxed Address and Data Bus For High Bandwidth
– 2 SP x SP → DP Every Two Clocks
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 22 Seite 66
- ・ Abmessungen des Paketumrisses on Seite 243 Seite 244
- ・ Markierungsinformationen on Seite 243 Seite 244
- ・ Blockdiagramm on Seite 4 Seite 9 Seite 116 Seite 117 Seite 118
- ・ Technische Daten on Seite 70 Seite 71 Seite 72 Seite 73 Seite 74
- ・ Anwendungsbereich on Seite 3 Seite 248
- ・ Elektrische Spezifikation on Seite 75 Seite 76 Seite 77 Seite 78 Seite 79
