herunterladen
TMS320C6748
www.ti.com
SPRS590C–JUNE 2009– REVISED JUNE 2011
TMS320C6748 Fixed/Floating-Point DSP
Check for Samples: TMS320C6748
1 TMS320C6748 Fixed/Floating-Point DSP
1.1 Features
12
• Highlights • TMS320C674x Floating-Point VLIW DSP Core
– 375/456-MHz C674x Fixed/Floating-Point – Load-Store Architecture With Non-Aligned
VLIW DSP Support
– Supports TI’s Basic Secure Boot – 64 General-Purpose Registers (32 Bit)
– Enhanced Direct-Memory-Access Controller – Six ALU (32-/40-Bit) Functional Units
(EDMA3)
• Supports 32-Bit Integer, SP (IEEE Single
– Serial ATA (SATA) Controller Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
– DDR2/Mobile DDR Memory Controller
• Supports up to Four SP Additions Per
– Two Multimedia Card (MMC)/Secure Digital
Clock, Four DP Additions Every 2 Clocks
(SD) Card Interface
• Supports up to Two Floating Point (SP or
– LCD Controller
DP) Reciprocal Approximation (RCPxP)
– Video Port Interface (VPIF)
and Square-Root Reciprocal
– 10/100 Mb/s Ethernet MAC (EMAC)
Approximation (RSQRxP) Operations Per
– Programmable Real-Time Unit Subsystem
Cycle
– Three Configurable UART Modules
– Two Multiply Functional Units
– USB 1.1 OHCI (Host) With Integrated PHY
• Mixed-Precision IEEE Floating Point
– USB 2.0 OTG Port With Integrated PHY
Multiply Supported up to:
– One Multichannel Audio Serial Port
– 2 SP x SP → SP Per Clock
– Two Multichannel Buffered Serial Ports
– 2 SP x SP → DP Every Two Clocks
• 375/456-MHz C674x Fixed/Floating-Point VLIW
– 2 SP x DP → DP Every Three Clocks
DSP
– 2 DP x DP → DP Every Four Clocks
• C674x™ Instruction Set Features
• Fixed Point Multiply Supports Two 32 x
– Superset of the C67x+™ and C64x+™ ISAs
32-Bit Multiplies, Four 16 x 16-Bit
– Up to 3648/2746 C674x MIPS/MFLOPS
Multiplies, or Eight 8 x 8-Bit Multiplies per
Clock Cycle, and Complex Multiples
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– Instruction Packing Reduces Code Size
– 8-Bit Overflow Protection
– All Instructions Conditional
– Bit-Field Extract, Set, Clear
– Hardware Support for Modulo Loop
– Normalization, Saturation, Bit-Counting
Operation
– Compact 16-Bit Instructions
– Protected Mode Operation
• C674x Two Level Cache Memory Architecture
– Exceptions Support for Error Detection and
– 32K-Byte L1P Program RAM/Cache
Program Redirection
– 32K-Byte L1D Data RAM/Cache
• Software Support
– 256K-Byte L2 Unified Mapped RAM/Cache
– TI DSP/BIOS™
– Flexible RAM/Cache Partition (L1 and L2)
– Chip Support Library and DSP Library
• Enhanced Direct-Memory-Access Controller 3
• 128K-Byte RAM Memory
(EDMA3):
• 1.8V or 3.3V LVCMOS IOs (except for USB and
– 2 Channel Controllers
DDR2 interfaces)
– 3 Transfer Controllers
• Two External Memory Interfaces:
– 64 Independent DMA Channels
– EMIFA
– 16 Quick DMA Channels
• NOR (8-/16-Bit-Wide Data)
– Programmable Transfer Burst Size
• NAND (8-/16-Bit-Wide Data)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
