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1 TMS320DM6437 Digital Media Processor
1.1 Features
TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
– 256K-Bit (32K-Byte) L1P Program
• High-Performance Digital Media Processor
RAM/Cache [Flexible Allocation]
(DM6437)
– 2.5-, 2.-, 1.67-, 1.51-, 1.43-ns Instruction
Cycle Time
– 640K-Bit (80K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
– 400-, 500-, 600, 660-, 700-MHz C64x+™
Clock Rate
– 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
– Eight 32-Bit C64x+ Instructions/Cycle
– 3200, 4000, 4800, 5280, 5600 MIPS
• Supports Little Endian Mode Only
– Fully Software-Compatible With C64x
• Video Processing Subsystem (VPSS)
– Commercial and Automotive (Q or S suffix)
– Front End Provides:
Grades
• CCD and CMOS Imager Interface
– Low-Power Device (L suffix)
• BT.601/BT.656 Digital YCbCr 4:2:2
• VelociTI.2™ Extensions to VelociTI™
(8-/16-Bit) Interface
Advanced Very-Long-Instruction-Word (VLIW)
• Preview Engine for Real-Time Image
TMS320C64x+™ DSP Core Processing
– Eight Highly Independent Functional Units • Glueless Interface to Common Video
With VelociTI.2 Extensions: Decoders
• Six ALUs (32-/40-Bit), Each Supports • Histogram Module
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
• Auto-Exposure, Auto-White Balance and
Arithmetic per Clock Cycle
Auto-Focus Module
• Two Multipliers Support Four 16 x 16-Bit
• Resize Engine
Multiplies (32-Bit Results) per Clock
– Resize Images From 1/4x to 4x
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
– Separate Horizontal/Vertical Control
Results) per Clock Cycle
– Back End Provides:
– Load-Store Architecture With Non-Aligned
• Hardware On-Screen Display (OSD)
Support
• Four 54-MHz DACs for a Combination of
– 64 32-Bit General-Purpose Registers
– Composite NTSC/PAL Video
– Instruction Packing Reduces Code Size
– Luma/Chroma Separate Video
– All Instructions Conditional
(S-video)
– Additional C64x+™ Enhancements
– Component (YPbPr or RGB) Video
• Protected Mode Operation
(Progressive)
• Exceptions Support for Error Detection
• Digital Output
and Program Redirection
– 8-/16-bit YUV or up to 24-Bit RGB
• Hardware Support for Modulo Loop
– HD Resolution
Auto-Focus Module Operation
– Up to 2 Video Windows
• C64x+ Instruction Set Features
• External Memory Interfaces (EMIFs)
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 32-Bit DDR2 SDRAM Memory Controller
– 8-Bit Overflow Protection
With 256M-Byte Address Space (1.8-V I/O)
– Bit-Field Extract, Set, Clear
• Supports up to 333-MHz (data rate) Bus
– Normalization, Saturation, Bit-Counting
and Interfaces With DDR2-400 SDRAM
– VelociTI.2 Increased Orthogonality
– Asynchronous 8-Bit Wide EMIF (EMIFA)
– C64x+ Extensions
With up to 64M-Byte Address Reach
• Compact 16-bit Instructions
• Flash Memory Interfaces
• Additional Instructions to Support
– NOR (8-Bit-Wide Data)
Complex Multiplies
– NAND (8-Bit-Wide Data)
• C64x+ L1/L2 Memory Architecture
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 17 Seite 30 Seite 34 Seite 38 Seite 40
- ・ Abmessungen des Paketumrisses on Seite 301 Seite 302
- ・ Markierungsinformationen on Seite 301 Seite 302
- ・ Blockdiagramm on Seite 5 Seite 156 Seite 157 Seite 166 Seite 167
- ・ Beschreibung der Funktionen on Seite 264
- ・ Technische Daten on Seite 158 Seite 160 Seite 162 Seite 163 Seite 164
- ・ Anwendungsbereich on Seite 2 Seite 159
- ・ Elektrische Spezifikation on Seite 154 Seite 160 Seite 161 Seite 162 Seite 163
