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TMS320F28069
,
TMS320F28068
,
TMS320F28067
,
TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698E –NOVEMBER 2010–REVISED JULY 2014
TMS320F2806x Piccolo™ Microcontrollers
1 Device Overview
1.1 Features
1
• High-Efficiency 32-Bit CPU (TMS320C28x) • Three 32-Bit CPU Timers
– 90 MHz (11.11-ns Cycle Time) • Advanced Control Peripherals
– 16 x 16 and 32 x 32 Multiply and Accumulate • Up to 8 Enhanced Pulse-Width Modulator (ePWM)
(MAC) Operations Modules
– 16 x 16 Dual MAC – 16 PWM Channels Total (8 HRPWM-Capable)
– Harvard Bus Architecture – Independent 16-Bit Timer in Each Module
– Atomic Operations • Three Input Enhanced Capture (eCAP) Modules
– Fast Interrupt Response and Processing • Up to 4 High-Resolution Capture (HRCAP)
Modules
– Unified Memory Programming Model
• Up to 2 Enhanced Quadrature Encoder Pulse
– Code-Efficient (in C/C++ and Assembly)
(eQEP) Modules
• Floating-Point Unit (FPU)
• 12-Bit Analog-to-Digital Converter (ADC), Dual
– Native Single-Precision Floating-Point
Sample-and-Hold (S/H)
Operations
– Up to 3.46 MSPS
• Programmable Control Law Accelerator (CLA)
– Up to 16 Channels
– 32-Bit Floating-Point Math Accelerator
• On-Chip Temperature Sensor
– Executes Code Independently of the Main CPU
• 128-Bit Security Key and Lock
• Viterbi, Complex Math, CRC Unit (VCU)
– Protects Secure Memory Blocks
– Extends C28x Instruction Set to Support
– Prevents Reverse-Engineering of Firmware
Complex Multiply, Viterbi Operations, and Cyclic
Redundency Check (CRC) • Serial Port Peripherals
• Embedded Memory – Two Serial Communications Interface (SCI)
[UART] Modules
– Up to 256KB of Flash
– Two Serial Peripheral Interface (SPI) Modules
– Up to 100KB of RAM
– One Inter-Integrated-Circuit (I
2
C) Bus
– 2KB of One-Time Programmable (OTP) ROM
– One Multichannel Buffered Serial Port (McBSP)
• 6-Channel Direct Memory Access (DMA)
Bus
• Low Device and System Cost
– One Enhanced Controller Area Network (eCAN)
– Single 3.3-V Supply
– Universal Serial Bus (USB) 2.0
– No Power Sequencing Requirement
(see Device Comparison Table for Availability)
– Integrated Power-on Reset and Brown-out
• Full-Speed Device Mode
Reset
• Full-Speed or Low-Speed Host Mode
– Low-Power Operating Modes
• Up to 54 Individually Programmable, Multiplexed
– No Analog Support Pin
General-Purpose Input/Output (GPIO) Pins With
• Endianness: Little Endian
Input Filtering
• JTAG Boundary Scan Support
• Advanced Emulation Features
– IEEE Standard 1149.1-1990 Standard Test
– Analysis and Breakpoint Functions
Access Port and Boundary Scan Architecture
– Real-Time Debug via Hardware
• Clocking
• 2806x Packages
– Two Internal Zero-Pin Oscillators
– 80-Pin PFP and 100-Pin PZP PowerPAD™
– On-Chip Crystal Oscillator/External Clock Input
Thermally Enhanced Thin Quad Flatpacks
– Watchdog Timer Module
(HTQFPs)
– Missing Clock Detection Circuitry
– 80-Pin PN and 100-Pin PZ Low-Profile Quad
• Peripheral Interrupt Expansion (PIE) Block That
Flatpacks (LQFPs)
Supports All Peripheral Interrupts
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 84
- ・ Abmessungen des Paketumrisses on Seite 171 Seite 172 Seite 173 Seite 174
- ・ Markierungsinformationen on Seite 171 Seite 172 Seite 173 Seite 174 Seite 175
- ・ Blockdiagramm on Seite 3 Seite 82 Seite 96 Seite 101 Seite 110
- ・ Typisches Anwendungsschaltbild on Seite 49 Seite 99
- ・ Technische Daten on Seite 22 Seite 23 Seite 24 Seite 25 Seite 26
- ・ Anwendungsbereich on Seite 2 Seite 74 Seite 135 Seite 139 Seite 176
- ・ Elektrische Spezifikation on Seite 23 Seite 88 Seite 97
