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Programmable Frequency Sweep and
Output Burst Waveform Generator
Data Sheet
AD5930
Rev. C Document Feedback
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FEATURES
Programmable frequency profile
No external components necessary
Output frequency up to 25 MHz
Burst and listen capability
Preprogrammable frequency profile minimizes number of
DSP/µcontroller writes
Sinusoidal/triangular/square wave outputs
Automatic or single pin control of frequency stepping
Waveform starts at known phase
Increments at 0° phase or phase continuously
Power-down mode: 20 µA
Power supply: 2.3 V to 5.5 V
Automotive temperature range: −40°C to +125°C
20-lead pb-free TSSOP
APPLICATIONS
Frequency sweeping/radar
Network/impedance measurements
Incremental frequency stimulus
Sensory applications
Proximity and motion
BFSK
Frequency bursting/pulse trains
GENERAL DESCRIPTION
The AD5930
1
is a waveform generator with programmable
frequency sweep and output burst capability. Utilizing
embedded digital processing that allows enhanced frequency
control, the device generates synthesized analog or digital
frequency-stepped waveforms. Because frequency profiles
are preprogrammed, continuous write cycles are eliminated
and thereby free up valuable DSP/µcontroller resources.
Waveforms start from a known phase and are incremented
phase continuously, which allows phase shifts to be easily
determined. Consuming only 8 mA, the AD5930 provides a
convenient low power solution to waveform generation.
The AD5930 can be operated in a variety of modes. In
continuous output mode, the device outputs the required
frequency for a defined length of time and then steps to the
next frequency. The length of time the device outputs a
particular frequency is either preprogrammed and the device
increments the frequency automatically, or, alternatively, is
incremented externally via the CTRL pin. In burst mode, the
device outputs its frequency for a length of time and then
returns to midscale for a further predefined length of time
before stepping to the next frequency. When the MSBOUT pin
is enabled, a digital output is generated.
(continued on Page 3)
FUNCTIONAL BLOCK DIAGRAM
CONTRO
L
REGISTER
D
ATA
24
INCR
SYNC
AND CONTROL
SYNCOUT
DGND O/P
MSBOUT
IOUTB
IOUT
COMP
MCLK
CTRL
INCREMENT
CONTROLLER
FREQUENCY
CONTROLLER
SERIAL INTERF
ACE
OUTPUT BURST
CONTROLLER
INTERRUPT
AD5930
S
TANDBY
DVDD CAP/2.5V DGND AGND AVDD
REF FSADJUST
24-BIT
PIPELINED
DDS CORE
DAT
A
DATA
SYNC
BUFFER
BUFFER
10-BIT
DAC
FSYNC SCLK SDATA
FULL-SCALE
CONTROL
ON-BOARD
REFERENCE
REGULAT
OR
VCC
2.5V
05333-001
Figure 1.
1
Protected by US Patent Number 6747583.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 12
- ・ Abmessungen des Paketumrisses on Seite 30
- ・ Teilenummerierungssystem on Seite 30
- ・ Blockdiagramm on Seite 1 Seite 28 Seite 29
- ・ Schweißen Temperatur on Seite 11
- ・ Beschreibung der Funktionen on Seite 1 Seite 6 Seite 12
- ・ Technische Daten on Seite 1 Seite 7 Seite 8 Seite 11 Seite 12
- ・ Anwendungsbereich on Seite 1 Seite 2 Seite 3 Seite 25
- ・ Elektrische Spezifikation on Seite 14
