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CDCEL824 Programmierhandbuch - TI

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CDCEL824
SCAS945A JUNE 2015REVISED SEPTEMBER 2015
CDCEL824 Programmable 2-PLL Clock Synthesizer
1 Features 2 Applications
Laser Distance Measurement Applications
1
Flexible Clock Driver
Three User-Definable Control Inputs
3 Description
[S0/S1/S2]: for example, Frequency Switching,
The CDCEL824 is a modular PLL-based low-cost,
Output Enable, or Power Down
high-performance, programmable clock synthesizer,
Enables 0-PPM Clock Generation
multiplier, and divider. It generates up to four output
In-System Programmability and EEPROM
clocks from a single input frequency. Each output can
be programmed in-system for any clock frequency up
Serial Programmable Volatile Register
to 201 MHz, using up to two independent
Nonvolatile EEPROM to Store Customer
configurable PLLs.
Settings
The CDCEL824 has a separate output supply pins,
Flexible Input Clocking Concept
V
DDOUT
, which are 1.8 V.
External Crystal: 20 MHz to 30 MHz
The input accepts an external crystal or LVCMOS
Single-Ended LVCMOS up to 130 MHz
clock signal. In case of a crystal input, an on-chip
Selectable Output Frequency up to 201 MHz
load capacitor is adequate for most applications. The
value of the load capacitor is programmable from
Low-Noise PLL Core
0 pF to 20 pF.
PLL Loop Filter Components Integrated
Low Period Jitter (Typical 80 ps)
Device Information
(1)
1.8-V Device Power Supply
PART NUMBER PACKAGE BODY SIZE (NOM)
Temperature Range –40°C to 85°C
CDCEL824 TSSOP (16) 5.00 mm x 4.40 mm
Packaged in TSSOP
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Verzeichnis

CDCEL824 Datenblatt-PDF

CDCEL824 Datenblatt PDF
TI
34 Seiten, 2015 KB
CDCEL824 Programmierhandbuch
TI
33 Seiten, 1853 KB
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