herunterladen
CY23FP12
200 MHz Field Programmable
Zero Delay Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-07246 Rev. *K Revised March 17, 2017
200 MHz Field Programmable Zero Delay Buffer
Features
■ Fully field-programmable
❐ Input and output dividers
❐ Inverting/non-inverting outputs
❐ Phase-locked loop (PLL) or fanout buffer configuration
■ 10 MHz to 200 MHz operating range
■ Split 2.5 V or 3.3 V outputs
■ Two LVCMOS reference inputs
■ Twelve low skew outputs
❐ 35 ps typical output-to-output skew (same frequency)
■ 110 ps typical cycle-cycle jitter (same frequency)
■ Three-stateable outputs
■ Less than 50 A shutdown current
■ Spread aware
■ 28-pin SSOP
■ 3.3 V operation
■ Industrial temperature available
Functional Description
The CY23FP12 is a high performance fully field-programmable
200 MHz zero delay buffer designed for high speed clock
distribution. The integrated PLL is designed for low jitter and
optimized for noise rejection. These parameters are critical for
reference clock distribution in systems using high performance
ASICs and microprocessors.
The CY23FP12 is fully programmable through volume or
prototype programmers, enabling the user to define an
application-specific Zero Delay Buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions listed in Table 2,
and assign a particular function set to any one of the four
possible S1-S2 control bit combinations. This feature enables
the implementation of four distinct personalities, selectable with
S1-S2 bits, on a single programmed silicon. The CY23FP12 also
features a proprietary auto power down circuit that shuts down
the device in case of a REF failure, resulting in less than 50 A
of current draw.
The CY23FP12 provides 12 outputs grouped in two banks with
separate power supply pins which can be connected
independently to either a 2.5 V or a 3.3 V rail.
Selectable reference input is a fault tolerance feature which
enables glitch-free switch over to a secondary clock source when
REFSEL is asserted/de-asserted.
For a complete list of related documentation, click here.
FBK
M
N
100 to
400MHz
PLL
CLKA1
CLKA3
CLKA2
REF2
REFSEL
CLKA4
CLKA5
CLKB1
CLKB3
CLKB2
CLKB4
CLKB5
VDDA
VSSA
VDDB
V
SS
B
2
3
4
X
CLKA0
VDDC
VSSC
1
Lock Detect
Test Logic
REF1
CLKB0
S
[
2:1
]
Function
Selection
Logic Block Diagram
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 3 Seite 4
- ・ Abmessungen des Paketumrisses on Seite 16
- ・ Teilenummerierungssystem on Seite 15
- ・ Blockdiagramm on Seite 1 Seite 5 Seite 8
- ・ Beschreibung der Funktionen on Seite 1 Seite 7
- ・ Technische Daten on Seite 10
- ・ Elektrische Spezifikation on Seite 10
