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Freescale Semiconductor
Application Note
© 2010-2012, 2014 Freescale Semiconductor, Inc. All rights reserved.
This application note expands on the description of the
double data rate (DDR3) memory controller programmable
registers in the PowerQUICC and QorIQ processor reference
manuals. The applicable device reference manual defines the
function of each field in the programmable registers. This
document focuses on why and when to select certain
configurations of the register bits and fields to achieve
efficient DDR programming. To obtain a comprehensive
understanding of the memory controller functionality and
the basic operation of the DDR3 memory, see the following
recommended documentation:
• Applicable reference manual
• Applicable device errata
• Applicable processor revision conversion guides
• Manufacturer data sheet on the memory selected
Many of the PowerQUICC and QorIQ documents are
available at the Freescale website listed on the back cover of
this document.
Document Number: AN4039
Rev. 4, 11/2014
Contents
1. Configuration guidelines . . . . . . . . . . . . . . . . . . . . . . . 2
2. Register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PowerQUICC and QorIQ
DDR3 SDRAM Controller Register
Setting Considerations
by Freescale Semiconductor, Inc.
Austin, TX
