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EN027 (v1.2) December 12, 2007 www.xilinx.com 1
Errata Notice
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Introduction
Thank you for your interest in the Xilinx Spartan™-3AN family XC3S50AN FPGA device engineering samples. Although Xil-
inx has made every effort to ensure the highest possible quality, these devices are subject to the limitations described in this
errata notification. These errata do not apply to the XC3S50AN production FPGAs.
Device Identification
These errata apply to the XC3S50AN engineering samples as shown in Ta bl e 1 . See the top-mark in Figure 1.
Traceability
XC3S50AN engineering samples are marked as shown in Figure 1. The other devices listed in Ta bl e 1 are marked similarly.
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Spartan-3AN XC3S50AN FPGA
Errata for Engineering Samples
EN027 (v1.2) December 12, 2007
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Errata Notice
Tabl e 1: XC3S50AN Devices Affected by These Errata
Device Types XC3S50AN
Packages All
Speed Grades -4
Date Codes All
Marked as "ES" Yes
Figure 1: XC3S50AN FPGA Top Marking
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