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TMS320C5517
SPRS727C AUGUST 2012REVISED APRIL 2014
TMS320C5517 Fixed-Point Digital Signal Processor
1 Device Overview
1.1 Features
1
Direct Memory Access (DMA) Controller
CORE:
Four DMA with Four Channels Each
High-Performance, Low-Power, TMS320C55x
Fixed-Point Digital Signal Processor
Three 32-Bit General-Purpose (GP) Timers
13.33- to 5-ns Instruction Cycle Time
One Selectable as a Watchdog or GP
75- to 200-MHz Clock Rate
Clocking Options, Including External
General-Purpose I/O (GPIO) Clock Input
One or Two Instructions Executed per Cycle
Two MultiMedia Card and Secure Digital
Dual Multiply-and-Accumulate Units (Up to
(eMMC, MMC, and SD) Interfaces
450 Million Multiply-Accumulates per Second
Serial Port Interface (SPI) with Four Chip
[MMACS])
Selects
Two Arithmetic and Logic Units (ALUs)
Master and Slave Inter-Integrated Circuit (I
2
C
Three Internal Data or Operand Read Buses
Bus)
and Two Write Buses
Three Inter-IC Sound (I
2
S Bus) Modules for
Software-Compatible with C55x Devices
Data Transport
Industrial Temperature Devices Available
10-Bit 4-Input Successive Approximation (SAR)
320KB of Zero-Wait State On-Chip RAM:
ADC
64KB of Dual-Access RAM (DARAM),
IEEE-1149.1 (JTAG)
8 Blocks of 4K x 16-Bit
Boundary-Scan-Compatible
256KB of Single-Access RAM (SARAM),
Up to 26 GPIO Pins (Multiplexed with Other
32 Blocks of 4K x 16-Bit
Functions)
128KB of Zero Wait-State On-Chip ROM
POWER:
(4 Blocks of 16K x 16-Bit)
Four Core Isolated Power Supply Domains:
Tightly Coupled FFT Hardware Accelerator
Analog, RTC, CPU and Peripherals, and USB
PERIPHERAL:
Four I/O Isolated Power Supply Domains: RTC
One Universal Host-Port Interface (UHPI) with
I/O, EMIF I/O, USB PHY, and DV
DDIO
16-Bit Muxed Address or Data Bus
1.05-V Core, 1.8-, 2.75-, or 3.3-V I/Os
Master and Slave Multichannel Serial Ports
1.3-V Core, 1.8-, 2.75-, or 3.3-V I/Os
Interface (McSPI) with Three Chip Selects
1.4-V Core, 1.8-, 2.75-, or 3.3-V I/Os
Master and Slave Multichannel Buffered Serial
CLOCK:
Ports Interface (McBSP)
Real-Time Clock (RTC) with Crystal Input,
16- and 8-Bit External Memory Interface (EMIF)
Separate Clock Domain, and Power Supply
with Glueless Interface to:
Software-Programmable Phase-Locked Loop
8- or 16-Bit NAND Flash, 1- or 4-Bit ECC
(PLL) Clock Generator
8- and 16-Bit NOR Flash
BOOTLOADER:
Asynchronous Static RAM (SRAM)
On-Chip ROM Bootloader
SDRAM or mSDRAM (1.8, 2.75, and 3.3 V)
Each Peripheral Supports Unencrypted
3.84375M x 16-Bit Maximum Addressable
Booting
External Memory Space (SDRAM or mSDRAM)
PACKAGE:
Universal Asynchronous Receiver/Transmitter
196-Terminal Pb-Free Plastic BGA (Ball Grid
(UART)
Array) (ZCH Suffix), 0.65-mm Pitch
Device USB Port with Integrated 2.0 High-
Speed PHY that Supports:
USB 2.0 Full- and High-Speed Devices
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Verzeichnis

TMS320C5517AZCHA20 Datenblatt-PDF

TMS320C5517AZCHA20 Benutzerreferenzhandbuch
TI
197 Seiten, 1257 KB
TMS320C5517AZCHA20 Anderes Datenblatt
TI
7 Seiten, 678 KB
TMS320C5517AZCHA20 Notizdatei
TI
9 Seiten, 696 KB

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