herunterladen
TMS320C6474
www.ti.com
SPRS552H–OCTOBER 2008– REVISED APRIL 2011
TMS320C6474 Multicore Digital Signal Processor
1 Features
12
• 1.2-GHz Device: -40°C to 95°C
(1)
• Key Features
• 1-GHz Device: -40°C to 100°C
– High-Performance Multicore DSP (C6474)
• 3 TMS320C64x+™ DSP Cores
– Instruction Cycle Time: 0.83 ns (1.2-GHz
Device); 1 ns (1-GHz Device); 1.18 ns – Dedicated SPLOOP Instructions
(850-MHz Device)
– Compact Instructions (16-Bit)
– Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz
– Exception Handling
Device); 1 GHz (1-GHz Device); 850 MHz
• TMS320C64x+ Megamodule L1 Memory
(850-MHz Device)
Architecture
– Commercial Temperature and Extended
– 256 K-Bit (32 K-Byte) L1P Program Cache
Temperature
[Direct Mapped]
– 3 TMS320C64x+™ DSP Cores; Six RSAs for
– 256 K-Bit (32 K-Byte) L1D Data Cache
CDMA Processing (2 per core)
[2-Way Set-Associative]
– Enhanced VCP2/TCP2
– 512 K-Bit (64 K-Byte) L3 ROM
– Frame Synchronization Interface
• Enhanced VCP2
– 16-/32-Bit DDR2-667 Memory Controller
– Supports Over 694 7.95-Kbps AMR
– EDMA3 Controller
• Enhanced Turbo Decoder Coprocessor (TCP2)
– Antenna Interface
– Supports up to Eight 2-Mbps 3 GPP
– Two 1x Serial RapidIO
®
Links, v1.2
(6 Iterations)
Compliant
• Endianness: Little Endian, Big Endian
– One 1.8-V Inter-Integrated Circuit (I2C) Bus
• Frame Synchronization Interface
– Two 1.8-V McBSPs
– Time Alignment Between Internal
– 1000 Mbps Ethernet MAC (EMAC)
Subsystems, External Devices/System
– Six 64-Bit General-Purpose Timers
– OBSAI RP1 Compliant for Frame Burst Data
– 16 General-Purpose I/O (GPIO) Pins
– Alternate Interfaces for non-RP1 and
– Internal Semaphore Module non-UMTS Systems
– System PLL and PLL Controller/DDR PLL • 16-/32-Bit DDR2-667 Memory Controller
and PLL Controller, Dedicated to DDR2
• EDMA3 Controller (64 Independent Channels)
Memory Controller
• Antenna Interface
• High-Performance Multicore DSP (C6474)
– 6 Configurable Links (Full Duplex)
– Instruction Cycle Time:
– Supports OBSAI RP3 Protocol, v1.0:
• 1.2-GHz Device: 0.83-ns
768-Mbps, 1.536-, 3.072-Gbps Link Rates
• 1-GHz Device: 1-ns
– Supports CPRI Protocol V2.0: 614.4-Mbps,
• 850-MHz Device: 1.18 ns 1.2288-, 2.4576-Gbps Link Rates
– Clock Rate: – Clock Input Independent or Shared with CPU
(Selectable at Boot-Time)
• 1.2-GHz Device: 1 GHz to 1.2 GHz
• Two 1x Serial RapidIO
®
Links, v1.2 Compliant
• 1-GHz Device: 1 GHz
– 1.25-, 2.5-, 3.125-Gbps Link Rates
• 850-MHz Device: 850 MHz
– Message Passing and DirectIO Support
– Eight 32-Bit Instructions/Cycle
– Error Management Extensions and
– Commercial Temperature:
Congestion Control
• 1.2-GHz Device: 0°C to 95°C
• One 1.8-V Inter-Integrated Circuit (I2C) Bus
• 850-MHZ and 1-GHz Device: 0°C to 100°C
• Two 1.8-V McBSPs
– Extended Temperature:
(1)
Note: Advance Information is presented in this document for
the C6474 1.2-GHz extended temperature device.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 17
- ・ Abmessungen des Paketumrisses on Seite 209 Seite 210
- ・ Markierungsinformationen on Seite 209 Seite 210
- ・ Blockdiagramm on Seite 5 Seite 53 Seite 56 Seite 58 Seite 130
- ・ Beschreibung der Funktionen on Seite 1 Seite 45
- ・ Technische Daten on Seite 72 Seite 74 Seite 75 Seite 76 Seite 77
- ・ Anwendungsbereich on Seite 157 Seite 215
- ・ Elektrische Spezifikation on Seite 73 Seite 74 Seite 75 Seite 76 Seite 77
- ・ Teilenummernliste on Seite 9
