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TMS320VC5505
www.ti.com
SPRS503B–JUNE 2009–REVISED JANUARY 2010
TMS320VC5505
Fixed-Point Digital Signal Processor
Check for Samples: TMS320VC5505
1 Fixed-Point Digital Signal Processor
1.1 TMS320VC5505 Features
1
• High-Performance, Low-Power, TMS320C55x™ • Device USB Port With Integrated 2.0
Fixed-Point Digital Signal Processor High-Speed PHY that Supports:
– 16.67-, 10-ns Instruction Cycle Time – USB 2.0 Full- and High-Speed Device
– 60-, 100-MHz Clock Rate • LCD Bridge With Asynchronous Interface
– One/Two Instruction(s) Executed per Cycle • Tightly-Coupled FFT Hardware Accelerator
– Dual Multipliers [Up to 200 Million • 10-Bit 4-Input Successive Approximation (SAR)
Multiply-Accumulates per Second (MMACS)] ADC
– Two Arithmetic/Logic Units (ALUs) • Real-Time Clock (RTC) With Crystal Input, With
Separate Clock Domain, Separate Power
– Three Internal Data/Operand Read Buses
Supply
and Two Internal Data/Operand Write Buses
• Four Core Isolated Power Supply Domains:
– Fully Software-Compatible With C55x
Analog, RTC, CPU and Peripherals, and USB
Devices
• Four I/O Isolated Power Supply Domains: RTC
– Industrial Temperature Devices Available
I/O, EMIF I/O, USB PHY, and DV
DDIO
• 320 K Bytes Zero-Wait State On-Chip RAM,
• Low-Power S/W Programmable Phase-Locked
Composed of:
Loop (PLL) Clock Generator
– 64K Bytes of Dual-Access RAM (DARAM),
• On-Chip ROM Bootloader (RBL) to Boot From
8 Blocks of 4K x 16-Bit
NAND Flash, NOR Flash, SPI EEPROM, or I2C
– 256K Bytes of Single-Access RAM (SARAM),
EEPROM
32 Blocks of 4K x 16-Bit
• IEEE-1149.1 (JTAG™)
• 128K Bytes of Zero Wait-State On-Chip ROM
Boundary-Scan-Compatible
(4 Blocks of 16K x 16-Bit)
• Up to 26 General-Purpose I/O (GPIO) Pins
• 16-/8-Bit External Memory Interface (EMIF) with
(Multiplexed With Other Device Functions)
Glueless Interface to:
• 196-Terminal Pb-Free Plastic BGA (Ball Grid
– 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
Array) (ZCH Suffix)
– 8-/16-Bit NOR Flash
• 1.05-V Core (60 MHz), 1.8-V, 2.5-V, 2.8-V, or
– Asynchronous Static RAM (SRAM)
3.3-V I/Os
• Direct Memory Access (DMA) Controller
• 1.3-V Core (100 MHz), 1.8-V, 2.5-V, 2.8-V, or
– Four DMA With 4 Channels Each
3.3-V I/Os
(16-Channels Total)
• Applications:
• Three 32-Bit General-Purpose Timers
– Wireless Audio Devices (e.g., Headsets,
– One Selectable as a Watchdog and/or GP
Microphones, Speakerphones, etc.)
• Two MultiMedia Card/Secure Digital (MMC/SD)
– Echo Cancellation Headphones
Interfaces
– Portable Medical Devices
• Universal Asynchronous Receiver/Transmitter
– Voice Applications
(UART)
– Industrial Controls
• Serial-Port Interface (SPI) With Four
– Fingerprint Biometrics
Chip-Selects
– Software Defined Radio
• Master/Slave Inter-Integrated Circuit (I
2
C Bus™)
• Community Resources
• Four Inter-IC Sound (I
2
S Bus™) for Data
– TI E2E Community
Transport
– TI Embedded Processors Wiki
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 12 Seite 44 Seite 48
- ・ Abmessungen des Paketumrisses on Seite 133
- ・ Markierungsinformationen on Seite 133
- ・ Blockdiagramm on Seite 3
- ・ Typisches Anwendungsschaltbild on Seite 114
- ・ Beschreibung der Funktionen on Seite 44
- ・ Technische Daten on Seite 10 Seite 53 Seite 57 Seite 58 Seite 59
- ・ Anwendungsbereich on Seite 1 Seite 136
- ・ Elektrische Spezifikation on Seite 10 Seite 29 Seite 33 Seite 52 Seite 55
