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PSoC
®
3: CY8C36 Family Datasheet
Programmable System-on-Chip (PSoC
®
)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-53413 Rev. *X Revised September 24, 2015
General Description
PSoC
®
3 is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a
microcontroller on a single chip. The PSoC 3 architecture boosts performance through:
8051 core plus DMA controller and digital filter processor, at up to 67 MHz
Ultra low power with industry's widest voltage range
Programmable digital and analog peripherals enable custom functions
Flexible routing of any analog or digital peripheral function to any pin
PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable
analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and
analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.
Features
Operating characteristics
Voltage range: 1.71 to 5.5 V, up to six power domains
Temperature range (ambient) –40 to 85 °C
[1]
DC to 67-MHz operation
Power modes
• Active mode 1.2 mA at 6 MHz, and 12 mA at 48 MHz
• 1-µA sleep mode
• 200-nA hibernate mode with RAM retention
Boost regulator from 0.5-V input up to 5-V output
Performance
8-bit 8051 CPU, 32 interrupt inputs
24-channel direct memory access (DMA) controller
24-bit 64-tap fixed-point digital filter processor (DFB)
Memories
Up to 64 KB program flash, with cache and security features
Up to 8 KB additional flash for error correcting code (ECC)
Up to 8 KB RAM
Up to 2 KB EEPROM
Digital peripherals
Up to four 16-bit timer, counter, and PWM (TCPWM) blocks
I
2
C, 1 Mbps bus speed
USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral
interface (TID#40770053) using internal oscillator
[2]
Full CAN 2.0b, 16 Rx, 8 Tx buffers
16 to 24 universal digital blocks (UDB), programmable to
create any number of functions:
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
•I
2
C, UART, SPI, I2S, LIN 2.0 interfaces
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generators
• Quadrature decoders
• Gate-level logic functions
Programmable clocking
3- to 62-MHz internal oscillator, 1% accuracy at 3 MHz
4- to 25-MHz external crystal oscillator
Internal PLL clock generation up to 67 MHz
Low-power internal oscillator at 1, 33, and 100 kHz
32.768-kHz external watch crystal oscillator
12 clock dividers routable to any peripheral or I/O
Analog peripherals
Configurable 8- to 12-bit delta-sigma ADC
Up to four 8-bit DACs
Up to four comparators
Up to four opamps
Up to four programmable analog blocks, to create:
• Programmable gain amplifier (PGA)
• Transimpedance amplifier (TIA)
•Mixer
• Sample and hold circuit
CapSense
®
support, up to 62 sensors
1.024 V ±0.1% internal voltage reference
Versatile I/O system
29 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)
Up to eight performance I/O (SIO) pins
• 25 mA current sink
• Programmable input threshold and output high voltages
• Can act as a general-purpose comparator
• Hot swap capability and overvoltage tolerance
Two USBIO pins that can be used as GPIOs
Route any digital or analog peripheral to any GPIO
LCD direct drive from any GPIO, up to 46 × 16 segments
CapSense support from any GPIO
1.2-V to 5.5-V interface voltages, up to four power domains
Programming and debug
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
Bootloader programming through I
2
C, SPI, UART, USB, and
other interfaces
Package options: 48-pin SSOP, 48-pin QFN, 68-pin QFN,
100-pin TQFP, and 72-pin WLCSP
Development support with free PSoC Creator™ tool
Schematic and firmware design support
Over 100 PSoC Components™ integrate multiple ICs and
system interfaces into one PSoC. Components are free
embedded ICs represented by icons. Drag and drop
component icons to design systems in PSoC Creator.
Includes free Keil 8051 compiler
Supports device programming and debugging
Notes
1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. This feature on select devices only. See Ordering Information on page 120 for details.
Verzeichnis
- ・ Konfiguration des Pinbelegungsdiagramms on Seite 12 Seite 24 Seite 54 Seite 94 Seite 130
- ・ Abmessungen des Paketumrisses on Seite 123 Seite 124
- ・ Teilenummerierungssystem on Seite 1 Seite 6 Seite 8 Seite 9 Seite 10
- ・ Blockdiagramm on Seite 1 Seite 4 Seite 11 Seite 25 Seite 30
- ・ Schweißen Temperatur on Seite 122 Seite 132
- ・ Beschreibung der Funktionen on Seite 1 Seite 28 Seite 47 Seite 57 Seite 59
- ・ Technische Daten on Seite 43 Seite 54 Seite 65 Seite 71 Seite 72
- ・ Anwendungsbereich on Seite 33 Seite 65
- ・ Elektrische Spezifikation on Seite 54 Seite 71 Seite 131
- ・ Teilenummernliste on Seite 71
